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Kernel: Implement {enable,disable}_msix interrupts in PCI Device
Implement enabling and disabling MSIx interrupts for a PCI device. Removes two TODO()s from PCI::Device.cpp :^)
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parent
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commit
bf7ac06d7b
Notes:
sideshowbarker
2024-07-16 23:34:49 +09:00
Author: https://github.com/Panky-codes Commit: https://github.com/SerenityOS/serenity/commit/bf7ac06d7b Pull-request: https://github.com/SerenityOS/serenity/pull/18580 Reviewed-by: https://github.com/gmta ✅ Reviewed-by: https://github.com/kleinesfilmroellchen Reviewed-by: https://github.com/supercomputer7 ✅
2 changed files with 12 additions and 2 deletions
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@ -82,6 +82,8 @@ static constexpr u32 bar_address_mask = 0xfffffff0;
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static constexpr u16 msix_control_table_mask = 0x07ff;
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static constexpr u8 msix_table_bir_mask = 0x7;
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static constexpr u16 msix_table_offset_mask = 0xfff8;
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static constexpr u8 msi_control_offset = 2;
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static constexpr u16 msix_control_enable = 0x8000;
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// Taken from https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf
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enum class ClassID {
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@ -44,13 +44,21 @@ void Device::disable_message_signalled_interrupts()
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{
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TODO();
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}
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void Device::enable_extended_message_signalled_interrupts()
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{
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TODO();
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for (auto& capability : m_pci_identifier->capabilities()) {
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if (capability.id().value() == PCI::Capabilities::ID::MSIX)
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capability.write16(msi_control_offset, capability.read16(msi_control_offset) | msix_control_enable);
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}
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}
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void Device::disable_extended_message_signalled_interrupts()
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{
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TODO();
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for (auto& capability : m_pci_identifier->capabilities()) {
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if (capability.id().value() == PCI::Capabilities::ID::MSIX)
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capability.write16(msi_control_offset, capability.read16(msi_control_offset) & ~(msix_control_enable));
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}
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}
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}
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