diff --git a/Kernel/Bus/PCI/Definitions.h b/Kernel/Bus/PCI/Definitions.h
index 4825268dec1..e1f085b85d8 100644
--- a/Kernel/Bus/PCI/Definitions.h
+++ b/Kernel/Bus/PCI/Definitions.h
@@ -82,6 +82,8 @@ static constexpr u32 bar_address_mask = 0xfffffff0;
 static constexpr u16 msix_control_table_mask = 0x07ff;
 static constexpr u8 msix_table_bir_mask = 0x7;
 static constexpr u16 msix_table_offset_mask = 0xfff8;
+static constexpr u8 msi_control_offset = 2;
+static constexpr u16 msix_control_enable = 0x8000;
 
 // Taken from https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf
 enum class ClassID {
diff --git a/Kernel/Bus/PCI/Device.cpp b/Kernel/Bus/PCI/Device.cpp
index 83805efd045..3eb7551a702 100644
--- a/Kernel/Bus/PCI/Device.cpp
+++ b/Kernel/Bus/PCI/Device.cpp
@@ -44,13 +44,21 @@ void Device::disable_message_signalled_interrupts()
 {
     TODO();
 }
+
 void Device::enable_extended_message_signalled_interrupts()
 {
-    TODO();
+    for (auto& capability : m_pci_identifier->capabilities()) {
+        if (capability.id().value() == PCI::Capabilities::ID::MSIX)
+            capability.write16(msi_control_offset, capability.read16(msi_control_offset) | msix_control_enable);
+    }
 }
+
 void Device::disable_extended_message_signalled_interrupts()
 {
-    TODO();
+    for (auto& capability : m_pci_identifier->capabilities()) {
+        if (capability.id().value() == PCI::Capabilities::ID::MSIX)
+            capability.write16(msi_control_offset, capability.read16(msi_control_offset) & ~(msix_control_enable));
+    }
 }
 
 }