8042ae43c3
It became apparent to me that future generations of the Intel graphics chipset utilize the same register set as part of the Transcoder register set. Therefore, it should be included now in the Transcoder class.
118 lines
3.7 KiB
C++
118 lines
3.7 KiB
C++
/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/RefPtr.h>
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#include <AK/Try.h>
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#include <AK/Types.h>
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#include <Kernel/Graphics/DisplayConnector.h>
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#include <Kernel/Graphics/Intel/Definitions.h>
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#include <Kernel/Locking/Spinlock.h>
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#include <Kernel/Memory/TypedMapping.h>
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namespace Kernel {
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class IntelDisplayConnectorGroup;
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class IntelDisplayTranscoder {
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public:
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// Note: This is used to "cache" all the registers we wrote to, because
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// we might not be able to read them directly from hardware later.
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struct ShadowRegisters {
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u32 horizontal_total;
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u32 horizontal_blank;
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u32 horizontal_sync;
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u32 vertical_total;
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u32 vertical_blank;
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u32 vertical_sync;
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u32 exit_line;
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u32 pipe_source;
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u32 pipe_border_color_pattern;
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u32 reserved;
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u32 vsync_shift;
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u32 pipe_mult;
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u32 dpll_reserved_dac_multiplier;
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u32 dpll_raw_dac_multiplier;
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u32 dpll_divisor_a0;
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u32 dpll_divisor_a1;
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u32 dpll_p1;
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u32 dpll_control;
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u32 m1_value;
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u32 n1_value;
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u32 m2_value;
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u32 n2_value;
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u32 m1_link;
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u32 n1_link;
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u32 m2_link;
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u32 n2_link;
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u32 pipe_conf;
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};
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ErrorOr<void> set_mode_setting_timings(Badge<IntelDisplayConnectorGroup>, DisplayConnector::ModeSetting const&);
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virtual ErrorOr<void> set_dpll_settings(Badge<IntelDisplayConnectorGroup>, IntelGraphics::PLLSettings const& settings, size_t dac_multiplier) = 0;
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virtual ErrorOr<void> enable_dpll_without_vga(Badge<IntelDisplayConnectorGroup>) = 0;
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virtual ErrorOr<void> disable_dpll(Badge<IntelDisplayConnectorGroup>) = 0;
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ErrorOr<void> disable_pipe(Badge<IntelDisplayConnectorGroup>);
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ErrorOr<void> enable_pipe(Badge<IntelDisplayConnectorGroup>);
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bool pipe_enabled(Badge<IntelDisplayConnectorGroup>) const;
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ShadowRegisters current_registers_state() const;
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virtual ~IntelDisplayTranscoder() = default;
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protected:
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struct [[gnu::packed]] TranscoderRegisters {
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u32 horizontal_total;
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u32 horizontal_blank;
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u32 horizontal_sync;
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u32 vertical_total;
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u32 vertical_blank;
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u32 vertical_sync;
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u32 exit_line;
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u32 pipe_source;
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u32 pipe_border_color_pattern;
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u32 reserved;
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u32 vsync_shift;
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u32 pipe_mult;
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u32 m1_value;
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u32 n1_value;
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u32 m2_value;
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u32 n2_value;
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u32 m1_link;
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u32 n1_link;
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u32 m2_link;
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u32 n2_link;
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};
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struct [[gnu::packed]] PipeRegisters {
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u32 pipe_display_scan_line;
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u32 pipe_display_scan_line_count_range_compare;
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u32 pipe_configuration;
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u32 reserved;
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u32 pipe_gamma_correction_max_red;
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u32 pipe_gamma_correction_max_green;
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u32 pipe_gamma_correction_max_blue;
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u32 reserved2[2];
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u32 pipe_display_status;
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u32 reserved3[2];
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u32 display_arbitration_control;
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u32 display_fifo_watermark_control1;
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u32 display_fifo_watermark_control2;
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u32 display_fifo_watermark_control3;
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u32 pipe_frame_count_high;
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// Note: The specification calls this "Pipe Frame Count Low and Pixel Count"
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u32 pipe_frame_count_low;
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};
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IntelDisplayTranscoder(Memory::TypedMapping<TranscoderRegisters volatile>, Memory::TypedMapping<PipeRegisters volatile>);
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mutable Spinlock<LockRank::None> m_access_lock;
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ShadowRegisters m_shadow_registers {};
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Memory::TypedMapping<TranscoderRegisters volatile> m_transcoder_registers;
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Memory::TypedMapping<PipeRegisters volatile> m_pipe_registers;
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};
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}
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