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1f9d3a3523
There are now 2 separate classes for almost the same object type: - EnumerableDeviceIdentifier, which is used in the enumeration code for all PCI host controller classes. This is allowed to be moved and copied, as it doesn't support ref-counting. - DeviceIdentifier, which inherits from EnumerableDeviceIdentifier. This class uses ref-counting, and is not allowed to be copied. It has a spinlock member in its structure to allow safely executing complicated IO sequences on a PCI device and its space configuration. There's a static method that allows a quick conversion from EnumerableDeviceIdentifier to DeviceIdentifier while creating a NonnullRefPtr out of it. The reason for doing this is for the sake of integrity and reliablity of the system in 2 places: - Ensure that "complicated" tasks that rely on manipulating PCI device registers are done in a safe manner. For example, determining a PCI BAR space size requires multiple read and writes to the same register, and if another CPU tries to do something else with our selected register, then the result will be a catastrophe. - Allow the PCI API to have a united form around a shared object which actually holds much more data than the PCI::Address structure. This is fundamental if we want to do certain types of optimizations, and be able to support more features of the PCI bus in the foreseeable future. This patch already has several implications: - All PCI::Device(s) hold a reference to a DeviceIdentifier structure being given originally from the PCI::Access singleton. This means that all instances of DeviceIdentifier structures are located in one place, and all references are pointing to that location. This ensures that locking the operation spinlock will take effect in all the appropriate places. - We no longer support adding PCI host controllers and then immediately allow for enumerating it with a lambda function. It was found that this method is extremely broken and too much complicated to work reliably with the new paradigm being introduced in this patch. This means that for Volume Management Devices (Intel VMD devices), we simply first enumerate the PCI bus for such devices in the storage code, and if we find a device, we attach it in the PCI::Access method which will scan for devices behind that bridge and will add new DeviceIdentifier(s) objects to its internal Vector. Afterwards, we just continue as usual with scanning for actual storage controllers, so we will find a corresponding NVMe controllers if there were any behind that VMD bridge.
273 lines
11 KiB
C++
273 lines
11 KiB
C++
/*
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* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/ByteReader.h>
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#include <AK/Error.h>
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#include <AK/HashTable.h>
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#if ARCH(X86_64)
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# include <Kernel/Arch/x86_64/PCI/Controller/HostBridge.h>
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#endif
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#include <Kernel/Bus/PCI/Access.h>
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#include <Kernel/Bus/PCI/Controller/MemoryBackedHostBridge.h>
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#include <Kernel/Bus/PCI/Initializer.h>
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#include <Kernel/Debug.h>
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#include <Kernel/Firmware/ACPI/Definitions.h>
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#include <Kernel/Memory/MemoryManager.h>
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#include <Kernel/Memory/Region.h>
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#include <Kernel/Memory/TypedMapping.h>
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#include <Kernel/ProcessExposed.h>
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#include <Kernel/Sections.h>
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namespace Kernel::PCI {
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#define PCI_MMIO_CONFIG_SPACE_SIZE 4096
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static Access* s_access;
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Access& Access::the()
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{
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if (s_access == nullptr) {
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VERIFY_NOT_REACHED(); // We failed to initialize the PCI subsystem, so stop here!
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}
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return *s_access;
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}
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bool Access::is_initialized()
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{
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return (s_access != nullptr);
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}
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bool Access::is_hardware_disabled()
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{
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return g_pci_access_io_probe_failed;
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}
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bool Access::is_disabled()
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{
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return g_pci_access_is_disabled_from_commandline || g_pci_access_io_probe_failed;
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}
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UNMAP_AFTER_INIT bool Access::find_and_register_pci_host_bridges_from_acpi_mcfg_table(PhysicalAddress mcfg_table)
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{
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u32 length = 0;
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u8 revision = 0;
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{
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auto mapped_mcfg_table_or_error = Memory::map_typed<ACPI::Structures::SDTHeader>(mcfg_table);
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if (mapped_mcfg_table_or_error.is_error()) {
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dbgln("Failed to map MCFG table");
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return false;
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}
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auto mapped_mcfg_table = mapped_mcfg_table_or_error.release_value();
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length = mapped_mcfg_table->length;
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revision = mapped_mcfg_table->revision;
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}
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if (length == sizeof(ACPI::Structures::SDTHeader))
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return false;
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dbgln("PCI: MCFG, length: {}, revision: {}", length, revision);
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if (Checked<size_t>::addition_would_overflow(length, PAGE_SIZE)) {
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dbgln("Overflow when adding extra page to allocation of length {}", length);
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return false;
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}
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length += PAGE_SIZE;
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auto region_size_or_error = Memory::page_round_up(length);
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if (region_size_or_error.is_error()) {
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dbgln("Failed to round up length of {} to pages", length);
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return false;
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}
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auto mcfg_region_or_error = MM.allocate_kernel_region(mcfg_table.page_base(), region_size_or_error.value(), "PCI Parsing MCFG"sv, Memory::Region::Access::ReadWrite);
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if (mcfg_region_or_error.is_error())
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return false;
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auto& mcfg = *(ACPI::Structures::MCFG*)mcfg_region_or_error.value()->vaddr().offset(mcfg_table.offset_in_page()).as_ptr();
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dbgln_if(PCI_DEBUG, "PCI: Checking MCFG @ {}, {}", VirtualAddress(&mcfg), mcfg_table);
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for (u32 index = 0; index < ((mcfg.header.length - sizeof(ACPI::Structures::MCFG)) / sizeof(ACPI::Structures::PCI_MMIO_Descriptor)); index++) {
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u8 start_bus = mcfg.descriptors[index].start_pci_bus;
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u8 end_bus = mcfg.descriptors[index].end_pci_bus;
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u64 start_addr = mcfg.descriptors[index].base_addr;
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Domain pci_domain { index, start_bus, end_bus };
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dmesgln("PCI: New PCI domain @ {}, PCI buses ({}-{})", PhysicalAddress { start_addr }, start_bus, end_bus);
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auto host_bridge = MemoryBackedHostBridge::must_create(pci_domain, PhysicalAddress { start_addr });
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add_host_controller(move(host_bridge));
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}
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return true;
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}
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UNMAP_AFTER_INIT bool Access::initialize_for_multiple_pci_domains(PhysicalAddress mcfg_table)
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{
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VERIFY(!Access::is_initialized());
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auto* access = new Access();
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if (!access->find_and_register_pci_host_bridges_from_acpi_mcfg_table(mcfg_table))
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return false;
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access->rescan_hardware();
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dbgln_if(PCI_DEBUG, "PCI: access for multiple PCI domain initialised.");
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return true;
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}
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#if ARCH(X86_64)
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UNMAP_AFTER_INIT bool Access::initialize_for_one_pci_domain()
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{
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VERIFY(!Access::is_initialized());
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auto* access = new Access();
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auto host_bridge = HostBridge::must_create_with_io_access();
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access->add_host_controller(move(host_bridge));
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access->rescan_hardware();
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dbgln_if(PCI_DEBUG, "PCI: access for one PCI domain initialised.");
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return true;
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}
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#endif
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ErrorOr<void> Access::add_host_controller_and_scan_for_devices(NonnullOwnPtr<HostController> controller)
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{
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SpinlockLocker locker(m_access_lock);
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SpinlockLocker scan_locker(m_scan_lock);
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auto domain_number = controller->domain_number();
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VERIFY(!m_host_controllers.contains(domain_number));
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// Note: We need to register the new controller as soon as possible, and
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// definitely before enumerating devices behind that.
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m_host_controllers.set(domain_number, move(controller));
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ErrorOr<void> error_or_void {};
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m_host_controllers.get(domain_number).value()->enumerate_attached_devices([&](EnumerableDeviceIdentifier const& device_identifier) -> IterationDecision {
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auto device_identifier_or_error = DeviceIdentifier::from_enumerable_identifier(device_identifier);
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if (device_identifier_or_error.is_error()) {
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error_or_void = device_identifier_or_error.error();
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return IterationDecision::Break;
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}
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m_device_identifiers.append(device_identifier_or_error.release_value());
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return IterationDecision::Continue;
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});
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return {};
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}
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UNMAP_AFTER_INIT void Access::add_host_controller(NonnullOwnPtr<HostController> controller)
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{
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auto domain_number = controller->domain_number();
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m_host_controllers.set(domain_number, move(controller));
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}
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UNMAP_AFTER_INIT Access::Access()
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{
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s_access = this;
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}
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UNMAP_AFTER_INIT void Access::rescan_hardware()
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{
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SpinlockLocker locker(m_access_lock);
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SpinlockLocker scan_locker(m_scan_lock);
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VERIFY(m_device_identifiers.is_empty());
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ErrorOr<void> error_or_void {};
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for (auto it = m_host_controllers.begin(); it != m_host_controllers.end(); ++it) {
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(*it).value->enumerate_attached_devices([this, &error_or_void](EnumerableDeviceIdentifier device_identifier) -> IterationDecision {
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auto device_identifier_or_error = DeviceIdentifier::from_enumerable_identifier(device_identifier);
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if (device_identifier_or_error.is_error()) {
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error_or_void = device_identifier_or_error.error();
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return IterationDecision::Break;
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}
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m_device_identifiers.append(device_identifier_or_error.release_value());
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return IterationDecision::Continue;
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});
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}
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if (error_or_void.is_error()) {
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dmesgln("Failed during PCI Access::rescan_hardware due to {}", error_or_void.error());
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VERIFY_NOT_REACHED();
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}
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}
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ErrorOr<void> Access::fast_enumerate(Function<void(DeviceIdentifier const&)>& callback) const
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{
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// Note: We hold the m_access_lock for a brief moment just to ensure we get
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// a complete Vector in case someone wants to mutate it.
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NonnullRefPtrVector<DeviceIdentifier> device_identifiers;
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{
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SpinlockLocker locker(m_access_lock);
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VERIFY(!m_device_identifiers.is_empty());
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TRY(device_identifiers.try_extend(m_device_identifiers));
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}
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for (auto const& device_identifier : device_identifiers) {
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callback(device_identifier);
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}
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return {};
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}
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DeviceIdentifier const& Access::get_device_identifier(Address address) const
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{
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for (auto& device_identifier : m_device_identifiers) {
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if (device_identifier.address().domain() == address.domain()
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&& device_identifier.address().bus() == address.bus()
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&& device_identifier.address().device() == address.device()
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&& device_identifier.address().function() == address.function()) {
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return device_identifier;
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}
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}
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VERIFY_NOT_REACHED();
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}
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void Access::write8_field(DeviceIdentifier const& identifier, u32 field, u8 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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SpinlockLocker locker(m_access_lock);
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VERIFY(m_host_controllers.contains(identifier.address().domain()));
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auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
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controller.write8_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field, value);
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}
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void Access::write16_field(DeviceIdentifier const& identifier, u32 field, u16 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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SpinlockLocker locker(m_access_lock);
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VERIFY(m_host_controllers.contains(identifier.address().domain()));
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auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
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controller.write16_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field, value);
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}
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void Access::write32_field(DeviceIdentifier const& identifier, u32 field, u32 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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SpinlockLocker locker(m_access_lock);
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VERIFY(m_host_controllers.contains(identifier.address().domain()));
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auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
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controller.write32_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field, value);
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}
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u8 Access::read8_field(DeviceIdentifier const& identifier, RegisterOffset field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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return read8_field(identifier, to_underlying(field));
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}
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u16 Access::read16_field(DeviceIdentifier const& identifier, RegisterOffset field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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return read16_field(identifier, to_underlying(field));
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}
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u8 Access::read8_field(DeviceIdentifier const& identifier, u32 field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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SpinlockLocker locker(m_access_lock);
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VERIFY(m_host_controllers.contains(identifier.address().domain()));
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auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
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return controller.read8_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field);
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}
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u16 Access::read16_field(DeviceIdentifier const& identifier, u32 field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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SpinlockLocker locker(m_access_lock);
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VERIFY(m_host_controllers.contains(identifier.address().domain()));
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auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
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return controller.read16_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field);
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}
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u32 Access::read32_field(DeviceIdentifier const& identifier, u32 field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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SpinlockLocker locker(m_access_lock);
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VERIFY(m_host_controllers.contains(identifier.address().domain()));
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auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
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return controller.read32_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field);
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}
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}
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