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Kernel/Graphics: Add basic support for Intel native accelerator
We simply modeset the resolution after determining the preferred resolution after getting the EDID from the attached display.
This commit is contained in:
Liav A
Andreas Kling
parent
6a728e2d76
commit
cc92538d49
Notes:
sideshowbarker
2024-07-18 18:01:05 +09:00
Author: https://github.com/supercomputer7 Commit: https://github.com/SerenityOS/serenity/commit/cc92538d49a Pull-request: https://github.com/SerenityOS/serenity/pull/6277 Reviewed-by: https://github.com/ElectrodeYT Reviewed-by: https://github.com/awesomekling
7 changed files with 882 additions and 0 deletions
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@ -54,6 +54,7 @@ set(KERNEL_SOURCES
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Graphics/BochsGraphicsAdapter.cpp
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Graphics/FramebufferDevice.cpp
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Graphics/GraphicsManagement.cpp
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Graphics/IntelNativeGraphicsAdapter.cpp
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Graphics/RawFramebufferDevice.cpp
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Graphics/VGACompatibleAdapter.cpp
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Storage/Partition/DiskPartition.cpp
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@ -102,6 +102,10 @@
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#cmakedefine01 ICMP_DEBUG
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#endif
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#ifndef INTEL_GRAPHICS_DEBUG
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#cmakedefine01 INTEL_GRAPHICS_DEBUG
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#endif
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#ifndef INTERRUPT_DEBUG
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#cmakedefine01 INTERRUPT_DEBUG
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#endif
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85
Kernel/Graphics/Definitions.h
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85
Kernel/Graphics/Definitions.h
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@ -0,0 +1,85 @@
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/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Types.h>
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namespace Kernel::Graphics {
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struct Timings {
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size_t blanking_start() const
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{
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return active;
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}
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size_t blanking_end() const
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{
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return total;
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}
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size_t active;
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size_t sync_start;
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size_t sync_end;
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size_t total;
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};
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struct Modesetting {
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size_t pixel_clock_in_khz;
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Timings horizontal;
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Timings vertical;
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};
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struct [[gnu::packed]] StandardTimings {
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u8 resolution;
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u8 frequency;
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};
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struct [[gnu::packed]] DetailTimings {
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u16 pixel_clock;
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u8 horizontal_active;
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u8 horizontal_blank;
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u8 horizontal_active_blank_msb;
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u8 vertical_active;
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u8 vertical_blank;
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u8 vertical_active_blank_msb;
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u8 horizontal_sync_offset;
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u8 horizontal_sync_pulse;
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u8 vertical_sync;
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u8 sync_msb;
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u8 dimension_width;
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u8 dimension_height;
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u8 dimension_msb;
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u8 horizontal_border;
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u8 vertical_border;
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u8 features;
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};
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struct [[gnu::packed]] VideoInfoBlock {
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u64 padding;
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u16 manufacture_id;
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u16 product_id;
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u32 serial_number;
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u8 manufacture_week;
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u8 manufacture_year;
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u8 edid_version;
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u8 edid_revision;
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u8 video_input_type;
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u8 max_horizontal_size;
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u8 max_vertical_size;
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u8 gama_factor;
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u8 dpms_flags;
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u8 chroma_info[10];
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u8 established_timing[2];
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u8 manufacture_reserved_timings;
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StandardTimings timings[8];
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DetailTimings details[4];
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u8 unused;
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u8 checksum;
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};
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static_assert(sizeof(VideoInfoBlock) == 128);
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}
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@ -10,6 +10,7 @@
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#include <Kernel/Debug.h>
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#include <Kernel/Graphics/BochsGraphicsAdapter.h>
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#include <Kernel/Graphics/GraphicsManagement.h>
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#include <Kernel/Graphics/IntelNativeGraphicsAdapter.h>
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#include <Kernel/Graphics/VGACompatibleAdapter.h>
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#include <Kernel/Multiboot.h>
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@ -38,6 +39,11 @@ UNMAP_AFTER_INIT RefPtr<GraphicsDevice> GraphicsManagement::determine_graphics_d
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return BochsGraphicsAdapter::initialize(address);
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}
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if (PCI::get_class(address) == 0x3 && PCI::get_subclass(address) == 0x0) {
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if (id.vendor_id == 0x8086) {
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auto adapter = IntelNativeGraphicsAdapter::initialize(address);
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if (!adapter.is_null())
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return adapter;
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}
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VERIFY(multiboot_info_ptr->framebuffer_type == MULTIBOOT_FRAMEBUFFER_TYPE_RGB || multiboot_info_ptr->framebuffer_type == MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT);
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return VGACompatibleAdapter::initialize_with_preset_resolution(address,
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PhysicalAddress((u32)(multiboot_info_ptr->framebuffer_addr)),
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605
Kernel/Graphics/IntelNativeGraphicsAdapter.cpp
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605
Kernel/Graphics/IntelNativeGraphicsAdapter.cpp
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@ -0,0 +1,605 @@
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/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Graphics/Definitions.h>
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#include <Kernel/Graphics/IntelNativeGraphicsAdapter.h>
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#include <Kernel/IO.h>
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#include <Kernel/PhysicalAddress.h>
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namespace Kernel {
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static constexpr IntelNativeGraphicsAdapter::PLLMaxSettings G35Limits {
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{ 20'000'000, 400'000'000 }, // values in Hz, dot_clock
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{ 1'400'000'000, 2'800'000'000 }, // values in Hz, VCO
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{ 3, 8 }, // n
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{ 70, 120 }, // m
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{ 10, 20 }, // m1
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{ 5, 9 }, // m2
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{ 5, 80 }, // p
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{ 1, 8 }, // p1
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{ 5, 10 } // p2
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};
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#define DDC2_I2C_ADDRESS 0x50
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RefPtr<IntelNativeGraphicsAdapter> IntelNativeGraphicsAdapter::initialize(PCI::Address address)
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{
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auto id = PCI::get_id(address);
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VERIFY(id.vendor_id == 0x8086);
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if (id.device_id != 0x29c2)
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return {};
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return adopt_ref(*new IntelNativeGraphicsAdapter(address));
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}
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static size_t compute_dac_multiplier(size_t pixel_clock_in_khz)
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{
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel native graphics: Pixel clock is {} KHz", pixel_clock_in_khz);
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VERIFY(pixel_clock_in_khz >= 25000);
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if (pixel_clock_in_khz >= 100000) {
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return 1;
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} else if (pixel_clock_in_khz >= 50000) {
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return 2;
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} else {
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return 4;
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}
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}
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static Graphics::Modesetting calculate_modesetting_from_edid(const Graphics::VideoInfoBlock& edid, size_t index)
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{
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Graphics::Modesetting mode;
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VERIFY(edid.details[0].pixel_clock);
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mode.pixel_clock_in_khz = edid.details[0].pixel_clock * 10;
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size_t horizontal_active = edid.details[index].horizontal_active | ((edid.details[index].horizontal_active_blank_msb >> 4) << 8);
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size_t horizontal_blank = edid.details[index].horizontal_blank | ((edid.details[index].horizontal_active_blank_msb & 0xF) << 8);
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size_t horizontal_sync_offset = edid.details[index].horizontal_sync_offset | ((edid.details[index].sync_msb >> 6) << 8);
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size_t horizontal_sync_pulse = edid.details[index].horizontal_sync_pulse | (((edid.details[index].sync_msb >> 4) & 0x3) << 8);
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mode.horizontal.active = horizontal_active;
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mode.horizontal.sync_start = horizontal_active + horizontal_sync_offset;
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mode.horizontal.sync_end = horizontal_active + horizontal_sync_offset + horizontal_sync_pulse;
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mode.horizontal.total = horizontal_active + horizontal_blank;
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size_t vertical_active = edid.details[index].vertical_active | ((edid.details[index].vertical_active_blank_msb >> 4) << 8);
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size_t vertical_blank = edid.details[index].vertical_blank | ((edid.details[index].vertical_active_blank_msb & 0xF) << 8);
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size_t vertical_sync_offset = (edid.details[index].vertical_sync >> 4) | (((edid.details[index].sync_msb >> 2) & 0x3) << 4);
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size_t vertical_sync_pulse = (edid.details[index].vertical_sync & 0xF) | ((edid.details[index].sync_msb & 0x3) << 4);
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mode.vertical.active = vertical_active;
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mode.vertical.sync_start = vertical_active + vertical_sync_offset;
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mode.vertical.sync_end = vertical_active + vertical_sync_offset + vertical_sync_pulse;
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mode.vertical.total = vertical_active + vertical_blank;
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return mode;
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}
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static bool check_pll_settings(const IntelNativeGraphicsAdapter::PLLSettings& settings, size_t reference_clock, const IntelNativeGraphicsAdapter::PLLMaxSettings& limits)
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{
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if (settings.n < limits.n.min || settings.n > limits.n.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "N is invalid {}", settings.n);
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return false;
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}
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if (settings.m1 < limits.m1.min || settings.m1 > limits.m1.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m1 is invalid {}", settings.m1);
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return false;
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}
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if (settings.m2 < limits.m2.min || settings.m2 > limits.m2.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m2 is invalid {}", settings.m2);
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return false;
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}
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if (settings.p1 < limits.p1.min || settings.p1 > limits.p1.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "p1 is invalid {}", settings.p1);
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return false;
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}
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if (settings.m1 <= settings.m2) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m2 is invalid {} as it is bigger than m1 {}", settings.m2, settings.m1);
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return false;
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}
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auto m = settings.compute_m();
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auto p = settings.compute_p();
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if (m < limits.m.min || m > limits.m.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m invalid {}", m);
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return false;
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}
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if (p < limits.p.min || p > limits.p.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "p invalid {}", p);
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return false;
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}
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auto dot = settings.compute_dot_clock(reference_clock);
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auto vco = settings.compute_vco(reference_clock);
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if (dot < limits.dot_clock.min || dot > limits.dot_clock.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Dot clock invalid {}", dot);
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return false;
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}
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if (vco < limits.vco.min || vco > limits.vco.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "VCO clock invalid {}", vco);
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return false;
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}
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return true;
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}
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static size_t find_absolute_difference(u64 target_frequency, u64 checked_frequency)
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{
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if (target_frequency >= checked_frequency)
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return target_frequency - checked_frequency;
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return checked_frequency - target_frequency;
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}
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Optional<IntelNativeGraphicsAdapter::PLLSettings> IntelNativeGraphicsAdapter::create_pll_settings(u64 target_frequency, u64 reference_clock, const PLLMaxSettings& limits)
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{
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IntelNativeGraphicsAdapter::PLLSettings settings;
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IntelNativeGraphicsAdapter::PLLSettings best_settings;
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// FIXME: Is this correct for all Intel Native graphics cards?
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settings.p2 = 10;
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Check PLL settings for ref clock of {} Hz, for target of {} Hz", reference_clock, target_frequency);
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u64 best_difference = 0xffffffff;
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for (settings.n = limits.n.min; settings.n <= limits.n.max; ++settings.n) {
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for (settings.m1 = limits.m1.max; settings.m1 >= limits.m1.min; --settings.m1) {
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for (settings.m2 = limits.m2.max; settings.m2 >= limits.m2.min; --settings.m2) {
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for (settings.p1 = limits.p1.max; settings.p1 >= limits.p1.min; --settings.p1) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Check PLL settings for {} {} {} {} {}", settings.n, settings.m1, settings.m2, settings.p1, settings.p2);
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if (!check_pll_settings(settings, reference_clock, limits))
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continue;
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auto current_dot_clock = settings.compute_dot_clock(reference_clock);
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if (current_dot_clock == target_frequency)
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return settings;
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auto difference = find_absolute_difference(target_frequency, current_dot_clock);
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if (difference < best_difference && (current_dot_clock > target_frequency)) {
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best_settings = settings;
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best_difference = difference;
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}
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}
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}
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}
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}
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if (best_settings.is_valid())
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return best_settings;
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return {};
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}
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IntelNativeGraphicsAdapter::IntelNativeGraphicsAdapter(PCI::Address address)
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: PCI::DeviceController(address)
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, m_registers(PCI::get_BAR0(address) & 0xfffffffc)
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, m_framebuffer_addr(PCI::get_BAR2(address) & 0xfffffffc)
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{
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel Native Graphics Adapter @ {}", address);
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auto bar0_space_size = PCI::get_BAR_space_size(address, 0);
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VERIFY(bar0_space_size == 0x80000);
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dmesgln("Intel Native Graphics Adapter @ {}, MMIO @ {}, space size is {:x} bytes", address, PhysicalAddress(PCI::get_BAR0(address)), bar0_space_size);
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dmesgln("Intel Native Graphics Adapter @ {}, framebuffer @ {}", address, PhysicalAddress(PCI::get_BAR2(address)));
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m_registers_region = MM.allocate_kernel_region(PhysicalAddress(PCI::get_BAR0(address)).page_base(), bar0_space_size, "Intel Native Graphics Registers", Region::Access::Read | Region::Access::Write);
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PCI::enable_bus_mastering(address);
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{
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ScopedSpinLock control_lock(m_control_lock);
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set_gmbus_default_rate();
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set_gmbus_pin_pair(GMBusPinPair::DedicatedAnalog);
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}
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gmbus_read_edid();
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auto modesetting = calculate_modesetting_from_edid(m_crt_edid, 0);
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dmesgln("Intel Native Graphics Adapter @ {}, preferred resolution is {:d}x{:d}", address, modesetting.horizontal.active, modesetting.vertical.active);
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set_crt_resolution(modesetting.horizontal.active, modesetting.vertical.active);
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}
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static inline const char* convert_register_index_to_string(IntelGraphics::RegisterIndex index)
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{
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switch (index) {
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case IntelGraphics::RegisterIndex::PipeAConf:
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return "PipeAConf";
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case IntelGraphics::RegisterIndex::PipeBConf:
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return "PipeBConf";
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case IntelGraphics::RegisterIndex::GMBusData:
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return "GMBusData";
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case IntelGraphics::RegisterIndex::GMBusStatus:
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return "GMBusStatus";
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case IntelGraphics::RegisterIndex::GMBusCommand:
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return "GMBusCommand";
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case IntelGraphics::RegisterIndex::GMBusClock:
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return "GMBusClock";
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case IntelGraphics::RegisterIndex::DisplayPlaneAControl:
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return "DisplayPlaneAControl";
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case IntelGraphics::RegisterIndex::DisplayPlaneALinearOffset:
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return "DisplayPlaneALinearOffset";
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case IntelGraphics::RegisterIndex::DisplayPlaneAStride:
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return "DisplayPlaneAStride";
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case IntelGraphics::RegisterIndex::DisplayPlaneASurface:
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return "DisplayPlaneASurface";
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case IntelGraphics::RegisterIndex::DPLLDivisorA0:
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return "DPLLDivisorA0";
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case IntelGraphics::RegisterIndex::DPLLDivisorA1:
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return "DPLLDivisorA1";
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case IntelGraphics::RegisterIndex::DPLLControlA:
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return "DPLLControlA";
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case IntelGraphics::RegisterIndex::DPLLControlB:
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return "DPLLControlB";
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case IntelGraphics::RegisterIndex::DPLLMultiplierA:
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return "DPLLMultiplierA";
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case IntelGraphics::RegisterIndex::HTotalA:
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return "HTotalA";
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case IntelGraphics::RegisterIndex::HBlankA:
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return "HBlankA";
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case IntelGraphics::RegisterIndex::HSyncA:
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return "HSyncA";
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case IntelGraphics::RegisterIndex::VTotalA:
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return "VTotalA";
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case IntelGraphics::RegisterIndex::VBlankA:
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return "VBlankA";
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case IntelGraphics::RegisterIndex::VSyncA:
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return "VSyncA";
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case IntelGraphics::RegisterIndex::PipeASource:
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return "PipeASource";
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case IntelGraphics::RegisterIndex::AnalogDisplayPort:
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return "AnalogDisplayPort";
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case IntelGraphics::RegisterIndex::VGADisplayPlaneControl:
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return "VGADisplayPlaneControl";
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default:
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VERIFY_NOT_REACHED();
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}
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}
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void IntelNativeGraphicsAdapter::write_to_register(IntelGraphics::RegisterIndex index, u32 value) const
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_registers_region);
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ScopedSpinLock lock(m_registers_lock);
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel Graphics {}: Write to {} value of {:x}", pci_address(), convert_register_index_to_string(index), value);
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auto* reg = (volatile u32*)m_registers_region->vaddr().offset(index).as_ptr();
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*reg = value;
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}
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u32 IntelNativeGraphicsAdapter::read_from_register(IntelGraphics::RegisterIndex index) const
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_registers_region);
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ScopedSpinLock lock(m_registers_lock);
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auto* reg = (volatile u32*)m_registers_region->vaddr().offset(index).as_ptr();
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u32 value = *reg;
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel Graphics {}: Read from {} value of {:x}", pci_address(), convert_register_index_to_string(index), value);
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return value;
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}
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bool IntelNativeGraphicsAdapter::pipe_a_enabled() const
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{
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VERIFY(m_control_lock.is_locked());
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return read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 30);
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}
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bool IntelNativeGraphicsAdapter::pipe_b_enabled() const
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{
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VERIFY(m_control_lock.is_locked());
|
||||
return read_from_register(IntelGraphics::RegisterIndex::PipeBConf) & (1 << 30);
|
||||
}
|
||||
|
||||
bool IntelNativeGraphicsAdapter::gmbus_wait_for(GMBusStatus desired_status, Optional<size_t> milliseconds_timeout)
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
size_t milliseconds_passed = 0;
|
||||
while (1) {
|
||||
if (milliseconds_timeout.has_value() && milliseconds_timeout.value() < milliseconds_passed)
|
||||
return false;
|
||||
full_memory_barrier();
|
||||
u32 status = read_from_register(IntelGraphics::RegisterIndex::GMBusStatus);
|
||||
full_memory_barrier();
|
||||
VERIFY(!(status & (1 << 10))); // error happened
|
||||
switch (desired_status) {
|
||||
case GMBusStatus::HardwareReady:
|
||||
if (status & (1 << 11))
|
||||
return true;
|
||||
break;
|
||||
case GMBusStatus::TransactionCompletion:
|
||||
if (status & (1 << 14))
|
||||
return true;
|
||||
break;
|
||||
default:
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
IO::delay(1000);
|
||||
milliseconds_passed++;
|
||||
}
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::gmbus_write(unsigned address, u32 byte)
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(address < 256);
|
||||
full_memory_barrier();
|
||||
write_to_register(IntelGraphics::RegisterIndex::GMBusData, byte);
|
||||
full_memory_barrier();
|
||||
write_to_register(IntelGraphics::RegisterIndex::GMBusCommand, ((address << 1) | (1 << 16) | (GMBusCycle::Wait << 25) | (1 << 30)));
|
||||
full_memory_barrier();
|
||||
gmbus_wait_for(GMBusStatus::TransactionCompletion, {});
|
||||
}
|
||||
void IntelNativeGraphicsAdapter::gmbus_read(unsigned address, u8* buf, size_t length)
|
||||
{
|
||||
VERIFY(address < 256);
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
size_t nread = 0;
|
||||
auto read_set = [&] {
|
||||
full_memory_barrier();
|
||||
u32 data = read_from_register(IntelGraphics::RegisterIndex::GMBusData);
|
||||
full_memory_barrier();
|
||||
for (size_t index = 0; index < 4; index++) {
|
||||
if (nread == length)
|
||||
break;
|
||||
buf[nread] = (data >> (8 * index)) & 0xFF;
|
||||
nread++;
|
||||
}
|
||||
};
|
||||
|
||||
full_memory_barrier();
|
||||
write_to_register(IntelGraphics::RegisterIndex::GMBusCommand, (1 | (address << 1) | (length << 16) | (GMBusCycle::Wait << 25) | (1 << 30)));
|
||||
full_memory_barrier();
|
||||
while (nread < length) {
|
||||
gmbus_wait_for(GMBusStatus::HardwareReady, {});
|
||||
read_set();
|
||||
}
|
||||
gmbus_wait_for(GMBusStatus::TransactionCompletion, {});
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::gmbus_read_edid()
|
||||
{
|
||||
ScopedSpinLock control_lock(m_control_lock);
|
||||
gmbus_write(DDC2_I2C_ADDRESS, 0);
|
||||
gmbus_read(DDC2_I2C_ADDRESS, (u8*)&m_crt_edid, sizeof(Graphics::VideoInfoBlock));
|
||||
}
|
||||
|
||||
bool IntelNativeGraphicsAdapter::is_resolution_valid(size_t, size_t)
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
// FIXME: Check that we are able to modeset to the requested resolution!
|
||||
return true;
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::disable_output()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
disable_dac_output();
|
||||
disable_all_planes();
|
||||
disable_pipe_a();
|
||||
disable_pipe_b();
|
||||
disable_vga_emulation();
|
||||
disable_dpll();
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::enable_output(PhysicalAddress fb_address, size_t width)
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(!pipe_a_enabled());
|
||||
|
||||
enable_pipe_a();
|
||||
enable_primary_plane(fb_address, width);
|
||||
enable_dac_output();
|
||||
}
|
||||
|
||||
bool IntelNativeGraphicsAdapter::set_crt_resolution(size_t width, size_t height)
|
||||
{
|
||||
ScopedSpinLock control_lock(m_control_lock);
|
||||
ScopedSpinLock modeset_lock(m_modeset_lock);
|
||||
if (!is_resolution_valid(width, height)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
// FIXME: Get the requested resolution from the EDID!!
|
||||
auto modesetting = calculate_modesetting_from_edid(m_crt_edid, 0);
|
||||
|
||||
disable_output();
|
||||
|
||||
auto dac_multiplier = compute_dac_multiplier(modesetting.pixel_clock_in_khz);
|
||||
auto pll_settings = create_pll_settings((1000 * modesetting.pixel_clock_in_khz * dac_multiplier), 96'000'000, G35Limits);
|
||||
if (!pll_settings.has_value())
|
||||
VERIFY_NOT_REACHED();
|
||||
auto settings = pll_settings.value();
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "PLL settings for {} {} {} {} {}", settings.n, settings.m1, settings.m2, settings.p1, settings.p2);
|
||||
set_dpll_registers(pll_settings.value(), dac_multiplier);
|
||||
set_display_timings(modesetting);
|
||||
auto address = PhysicalAddress(PCI::get_BAR2(pci_address()) & 0xfffffff0);
|
||||
VERIFY(!address.is_null());
|
||||
enable_output(address, width);
|
||||
|
||||
m_framebuffer_width = width;
|
||||
m_framebuffer_height = height;
|
||||
m_framebuffer_stride = width * 4;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::set_display_timings(const Graphics::Modesetting& modesetting)
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
VERIFY(!(read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 31)));
|
||||
VERIFY(!(read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 30)));
|
||||
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "htotal - {}, {}", (modesetting.horizontal.active - 1), (modesetting.horizontal.total - 1));
|
||||
write_to_register(IntelGraphics::RegisterIndex::HTotalA, (modesetting.horizontal.active - 1) | (modesetting.horizontal.total - 1) << 16);
|
||||
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "hblank - {}, {}", (modesetting.horizontal.blanking_start() - 1), (modesetting.horizontal.blanking_end() - 1));
|
||||
write_to_register(IntelGraphics::RegisterIndex::HBlankA, (modesetting.horizontal.blanking_start() - 1) | (modesetting.horizontal.blanking_end() - 1) << 16);
|
||||
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "hsync - {}, {}", (modesetting.horizontal.sync_start - 1), (modesetting.horizontal.sync_end - 1));
|
||||
write_to_register(IntelGraphics::RegisterIndex::HSyncA, (modesetting.horizontal.sync_start - 1) | (modesetting.horizontal.sync_end - 1) << 16);
|
||||
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "vtotal - {}, {}", (modesetting.vertical.active - 1), (modesetting.vertical.total - 1));
|
||||
write_to_register(IntelGraphics::RegisterIndex::VTotalA, (modesetting.vertical.active - 1) | (modesetting.vertical.total - 1) << 16);
|
||||
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "vblank - {}, {}", (modesetting.vertical.blanking_start() - 1), (modesetting.vertical.blanking_end() - 1));
|
||||
write_to_register(IntelGraphics::RegisterIndex::VBlankA, (modesetting.vertical.blanking_start() - 1) | (modesetting.vertical.blanking_end() - 1) << 16);
|
||||
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "vsync - {}, {}", (modesetting.vertical.sync_start - 1), (modesetting.vertical.sync_end - 1));
|
||||
write_to_register(IntelGraphics::RegisterIndex::VSyncA, (modesetting.vertical.sync_start - 1) | (modesetting.vertical.sync_end - 1) << 16);
|
||||
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "sourceSize - {}, {}", (modesetting.vertical.active - 1), (modesetting.horizontal.active - 1));
|
||||
write_to_register(IntelGraphics::RegisterIndex::PipeASource, (modesetting.vertical.active - 1) | (modesetting.horizontal.active - 1) << 16);
|
||||
|
||||
IO::delay(200);
|
||||
}
|
||||
|
||||
bool IntelNativeGraphicsAdapter::wait_for_enabled_pipe_a(size_t milliseconds_timeout) const
|
||||
{
|
||||
size_t current_time = 0;
|
||||
while (current_time < milliseconds_timeout) {
|
||||
if (pipe_a_enabled())
|
||||
return true;
|
||||
IO::delay(1000);
|
||||
current_time++;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
bool IntelNativeGraphicsAdapter::wait_for_disabled_pipe_a(size_t milliseconds_timeout) const
|
||||
{
|
||||
size_t current_time = 0;
|
||||
while (current_time < milliseconds_timeout) {
|
||||
if (!pipe_a_enabled())
|
||||
return true;
|
||||
IO::delay(1000);
|
||||
current_time++;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool IntelNativeGraphicsAdapter::wait_for_disabled_pipe_b(size_t milliseconds_timeout) const
|
||||
{
|
||||
size_t current_time = 0;
|
||||
while (current_time < milliseconds_timeout) {
|
||||
if (!pipe_b_enabled())
|
||||
return true;
|
||||
IO::delay(1000);
|
||||
current_time++;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::disable_dpll()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::DPLLControlA, read_from_register(IntelGraphics::RegisterIndex::DPLLControlA) & ~0x80000000);
|
||||
write_to_register(IntelGraphics::RegisterIndex::DPLLControlB, read_from_register(IntelGraphics::RegisterIndex::DPLLControlB) & ~0x80000000);
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::disable_pipe_a()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::PipeAConf, read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & ~0x80000000);
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe A");
|
||||
wait_for_disabled_pipe_a(100);
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe A - done.");
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::disable_pipe_b()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::PipeAConf, read_from_register(IntelGraphics::RegisterIndex::PipeBConf) & ~0x80000000);
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe B");
|
||||
wait_for_disabled_pipe_b(100);
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe B - done.");
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::set_gmbus_default_rate()
|
||||
{
|
||||
// FIXME: Verify GMBUS Rate Select is set only when GMBUS is idle
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
// Set the rate to 100KHz
|
||||
write_to_register(IntelGraphics::RegisterIndex::GMBusClock, read_from_register(IntelGraphics::RegisterIndex::GMBusClock) & ~(0b111 << 8));
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::enable_pipe_a()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
VERIFY(!(read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 31)));
|
||||
VERIFY(!(read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 30)));
|
||||
write_to_register(IntelGraphics::RegisterIndex::PipeAConf, read_from_register(IntelGraphics::RegisterIndex::PipeAConf) | 0x80000000);
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "enabling Pipe A");
|
||||
// FIXME: Seems like my video card is buggy and doesn't set the enabled bit (bit 30)!!
|
||||
wait_for_enabled_pipe_a(100);
|
||||
dbgln_if(INTEL_GRAPHICS_DEBUG, "enabling Pipe A - done.");
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::enable_primary_plane(PhysicalAddress fb_address, size_t width)
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
VERIFY(((width * 4) % 64 == 0));
|
||||
|
||||
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneAStride, width * 4);
|
||||
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneALinearOffset, 0);
|
||||
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneASurface, fb_address.get());
|
||||
|
||||
// FIXME: Serenity uses BGR 32 bit pixel format, but maybe we should try to determine it somehow!
|
||||
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneAControl, (read_from_register(IntelGraphics::RegisterIndex::DisplayPlaneAControl) & (~(0b1111 << 26))) | (0b0110 << 26) | (1 << 31));
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::set_dpll_registers(const PLLSettings& settings, size_t dac_multiplier)
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::DPLLDivisorA0, (settings.m2 - 2) | ((settings.m1 - 2) << 8) | ((settings.n - 2) << 16));
|
||||
write_to_register(IntelGraphics::RegisterIndex::DPLLDivisorA1, (settings.m2 - 2) | ((settings.m1 - 2) << 8) | ((settings.n - 2) << 16));
|
||||
|
||||
write_to_register(IntelGraphics::RegisterIndex::DPLLControlA, read_from_register(IntelGraphics::RegisterIndex::DPLLControlA) & ~0x80000000);
|
||||
|
||||
IO::delay(200);
|
||||
|
||||
write_to_register(IntelGraphics::RegisterIndex::DPLLControlA, (6 << 9) | (settings.p1) << 16 | (1 << 26) | (1 << 28) | (1 << 31));
|
||||
write_to_register(IntelGraphics::RegisterIndex::DPLLMultiplierA, (dac_multiplier - 1) | ((dac_multiplier - 1) << 8));
|
||||
|
||||
// The specification says we should wait (at least) about 150 microseconds
|
||||
// after enabling the DPLL to allow the clock to stabilize
|
||||
IO::delay(200);
|
||||
VERIFY(read_from_register(IntelGraphics::RegisterIndex::DPLLControlA) & (1 << 31));
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::set_gmbus_pin_pair(GMBusPinPair pin_pair)
|
||||
{
|
||||
// FIXME: Verify GMBUS is idle
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::GMBusClock, (read_from_register(IntelGraphics::RegisterIndex::GMBusClock) & (~0b111)) | (pin_pair & 0b111));
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::disable_dac_output()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::AnalogDisplayPort, 0b11 << 10);
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::enable_dac_output()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::AnalogDisplayPort, (read_from_register(IntelGraphics::RegisterIndex::AnalogDisplayPort) & (~(0b11 << 10))) | 0x80000000);
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::disable_vga_emulation()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::VGADisplayPlaneControl, (read_from_register(IntelGraphics::RegisterIndex::VGADisplayPlaneControl) & (~(1 << 30))) | 0x80000000);
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::disable_all_planes()
|
||||
{
|
||||
VERIFY(m_control_lock.is_locked());
|
||||
VERIFY(m_modeset_lock.is_locked());
|
||||
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneAControl, read_from_register(IntelGraphics::RegisterIndex::DisplayPlaneAControl) & ~(1 << 31));
|
||||
}
|
||||
|
||||
void IntelNativeGraphicsAdapter::initialize_framebuffer_devices()
|
||||
{
|
||||
auto address = PhysicalAddress(PCI::get_BAR2(pci_address()) & 0xfffffff0);
|
||||
VERIFY(!address.is_null());
|
||||
VERIFY(m_framebuffer_stride != 0);
|
||||
VERIFY(m_framebuffer_height != 0);
|
||||
VERIFY(m_framebuffer_width != 0);
|
||||
m_framebuffer = m_framebuffer = RawFramebufferDevice::create(*this, address, m_framebuffer_stride, m_framebuffer_width, m_framebuffer_height);
|
||||
}
|
||||
}
|
||||
180
Kernel/Graphics/IntelNativeGraphicsAdapter.h
Normal file
180
Kernel/Graphics/IntelNativeGraphicsAdapter.h
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <AK/String.h>
|
||||
#include <AK/Types.h>
|
||||
#include <Kernel/Graphics/Definitions.h>
|
||||
#include <Kernel/Graphics/GraphicsDevice.h>
|
||||
#include <Kernel/Graphics/RawFramebufferDevice.h>
|
||||
#include <Kernel/PCI/DeviceController.h>
|
||||
#include <Kernel/PhysicalAddress.h>
|
||||
|
||||
namespace Kernel {
|
||||
|
||||
namespace IntelGraphics {
|
||||
|
||||
enum RegisterIndex {
|
||||
PipeAConf = 0x70008,
|
||||
PipeBConf = 0x71008,
|
||||
GMBusData = 0x510C,
|
||||
GMBusStatus = 0x5108,
|
||||
GMBusCommand = 0x5104,
|
||||
GMBusClock = 0x5100,
|
||||
DisplayPlaneAControl = 0x70180,
|
||||
DisplayPlaneALinearOffset = 0x70184,
|
||||
DisplayPlaneAStride = 0x70188,
|
||||
DisplayPlaneASurface = 0x7019C,
|
||||
DPLLDivisorA0 = 0x6040,
|
||||
DPLLDivisorA1 = 0x6044,
|
||||
DPLLControlA = 0x6014,
|
||||
DPLLControlB = 0x6018,
|
||||
DPLLMultiplierA = 0x601C,
|
||||
HTotalA = 0x60000,
|
||||
HBlankA = 0x60004,
|
||||
HSyncA = 0x60008,
|
||||
VTotalA = 0x6000C,
|
||||
VBlankA = 0x60010,
|
||||
VSyncA = 0x60014,
|
||||
PipeASource = 0x6001C,
|
||||
AnalogDisplayPort = 0x61100,
|
||||
VGADisplayPlaneControl = 0x71400,
|
||||
};
|
||||
}
|
||||
|
||||
class IntelNativeGraphicsAdapter final
|
||||
: public GraphicsDevice
|
||||
, public PCI::DeviceController {
|
||||
AK_MAKE_ETERNAL
|
||||
public:
|
||||
struct PLLSettings {
|
||||
bool is_valid() const { return (n != 0 && m1 != 0 && m2 != 0 && p1 != 0 && p2 != 0); }
|
||||
u64 compute_dot_clock(u64 refclock) const
|
||||
{
|
||||
return (refclock * (5 * (m1) + (m2)) / (n)) / (p1 * p2);
|
||||
}
|
||||
|
||||
u64 compute_vco(u64 refclock) const
|
||||
{
|
||||
return refclock * (5 * (m1) + (m2)) / n;
|
||||
}
|
||||
|
||||
u64 compute_m() const
|
||||
{
|
||||
return 5 * (m1) + (m2);
|
||||
}
|
||||
|
||||
u64 compute_p() const
|
||||
{
|
||||
return p1 * p2;
|
||||
}
|
||||
u64 n { 0 };
|
||||
u64 m1 { 0 };
|
||||
u64 m2 { 0 };
|
||||
u64 p1 { 0 };
|
||||
u64 p2 { 0 };
|
||||
};
|
||||
struct PLLParameterLimit {
|
||||
size_t min, max;
|
||||
};
|
||||
struct PLLMaxSettings {
|
||||
PLLParameterLimit dot_clock, vco, n, m, m1, m2, p, p1, p2;
|
||||
};
|
||||
|
||||
private:
|
||||
enum GMBusPinPair : u8 {
|
||||
None = 0,
|
||||
DedicatedControl = 1,
|
||||
DedicatedAnalog = 0b10,
|
||||
IntegratedDigital = 0b11,
|
||||
sDVO = 0b101,
|
||||
Dconnector = 0b111,
|
||||
};
|
||||
|
||||
enum class GMBusStatus {
|
||||
TransactionCompletion,
|
||||
HardwareReady
|
||||
};
|
||||
|
||||
enum GMBusCycle {
|
||||
Wait = 1,
|
||||
Stop = 4,
|
||||
};
|
||||
|
||||
public:
|
||||
static RefPtr<IntelNativeGraphicsAdapter> initialize(PCI::Address);
|
||||
|
||||
private:
|
||||
explicit IntelNativeGraphicsAdapter(PCI::Address);
|
||||
|
||||
void write_to_register(IntelGraphics::RegisterIndex, u32 value) const;
|
||||
u32 read_from_register(IntelGraphics::RegisterIndex) const;
|
||||
|
||||
// ^GraphicsDevice
|
||||
virtual void initialize_framebuffer_devices() override;
|
||||
virtual Type type() const override { return Type::VGACompatible; }
|
||||
|
||||
bool pipe_a_enabled() const;
|
||||
bool pipe_b_enabled() const;
|
||||
|
||||
bool is_resolution_valid(size_t width, size_t height);
|
||||
|
||||
bool set_crt_resolution(size_t width, size_t height);
|
||||
|
||||
void disable_output();
|
||||
void enable_output(PhysicalAddress fb_address, size_t width);
|
||||
|
||||
void disable_vga_emulation();
|
||||
|
||||
void disable_dac_output();
|
||||
void enable_dac_output();
|
||||
|
||||
void disable_all_planes();
|
||||
void disable_pipe_a();
|
||||
void disable_pipe_b();
|
||||
void disable_dpll();
|
||||
|
||||
void set_dpll_registers(const PLLSettings&, size_t dac_multiplier);
|
||||
void set_display_timings(const Graphics::Modesetting&);
|
||||
void enable_pipe_a();
|
||||
void set_framebuffer_parameters(size_t, size_t);
|
||||
void enable_primary_plane(PhysicalAddress fb_address, size_t stride);
|
||||
|
||||
bool wait_for_enabled_pipe_a(size_t milliseconds_timeout) const;
|
||||
bool wait_for_disabled_pipe_a(size_t milliseconds_timeout) const;
|
||||
bool wait_for_disabled_pipe_b(size_t milliseconds_timeout) const;
|
||||
|
||||
void set_gmbus_default_rate();
|
||||
void set_gmbus_pin_pair(GMBusPinPair pin_pair);
|
||||
|
||||
// FIXME: It would be better if we generalize the I2C access later on
|
||||
void gmbus_read_edid();
|
||||
void gmbus_write(unsigned address, u32 byte);
|
||||
void gmbus_read(unsigned address, u8* buf, size_t length);
|
||||
bool gmbus_wait_for(GMBusStatus desired_status, Optional<size_t> milliseconds_timeout);
|
||||
|
||||
Optional<PLLSettings> create_pll_settings(u64 target_frequency, u64 reference_clock, const PLLMaxSettings&);
|
||||
|
||||
SpinLock<u8> m_control_lock;
|
||||
SpinLock<u8> m_modeset_lock;
|
||||
mutable SpinLock<u8> m_registers_lock;
|
||||
|
||||
Graphics::VideoInfoBlock m_crt_edid;
|
||||
const PhysicalAddress m_registers;
|
||||
const PhysicalAddress m_framebuffer_addr;
|
||||
|
||||
OwnPtr<Region> m_registers_region;
|
||||
|
||||
size_t m_framebuffer_width { 0 };
|
||||
size_t m_framebuffer_height { 0 };
|
||||
size_t m_framebuffer_stride { 0 };
|
||||
|
||||
protected:
|
||||
RefPtr<RawFramebufferDevice> m_framebuffer;
|
||||
};
|
||||
|
||||
}
|
||||
|
|
@ -136,6 +136,7 @@ set(HTTPSJOB_DEBUG ON)
|
|||
set(ICMP_DEBUG ON)
|
||||
set(ICO_DEBUG ON)
|
||||
set(IPV4_DEBUG ON)
|
||||
set(INTEL_GRAPHICS_DEBUG ON)
|
||||
set(IRC_DEBUG ON)
|
||||
set(KEYBOARD_DEBUG ON)
|
||||
set(LEXER_DEBUG ON)
|
||||
|
|
|
|||
Loading…
Reference in a new issue