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Kernel/riscv64: Don't flush the entire TLB in Processor::flush_tlb_local

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Sönke Holz 2024-04-21 12:52:25 +02:00 committed by Andrew Kaster
parent cf92efc497
commit c57e39d52b
Notes: sideshowbarker 2024-07-17 02:35:27 +09:00 
Author: https://github.com/spholz
Commit: https://github.com/SerenityOS/serenity/commit/c57e39d52b
Pull-request: https://github.com/SerenityOS/serenity/pull/24053
Reviewed-by: https://github.com/ADKaster ✅
1 changed files with 13 additions and 3 deletions
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16
Kernel/Arch/riscv64/Processor.cpp
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@ -137,10 +137,19 @@ template<typename T>
}
template<typename T>
void ProcessorBase<T>::flush_tlb_local(VirtualAddress, size_t)
void ProcessorBase<T>::flush_tlb_local(VirtualAddress vaddr, size_t page_count)
{
// FIXME: Don't flush all pages
flush_entire_tlb_local();
auto addr = vaddr.get();
while (page_count > 0) {
// clang-format off
asm volatile("sfence.vma %0"
:
: "r"(addr)
: "memory");
// clang-format on
addr += PAGE_SIZE;
page_count--;
}
}
template<typename T>
@ -152,6 +161,7 @@ void ProcessorBase<T>::flush_entire_tlb_local()
template<typename T>
void ProcessorBase<T>::flush_tlb(Memory::PageDirectory const*, VirtualAddress vaddr, size_t page_count)
{
// FIXME: Use the SBI RFENCE extension to flush the TLB of other harts when we support SMP on riscv64.
flush_tlb_local(vaddr, page_count);
}