fw/drivers/nrf5/qspi: reduce clock frequency

Communication errors have been observed, often leading to CRC errors.
This setting should actually be pushed to board level, better routing
may allow using higher frequencies.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

src/fw/drivers/nrf5/qspi.c

@@ -184,7 +184,7 @@ void qspi_flash_init(QSPIFlash *dev, QSPIFlashPart *part, bool coredump_mode) {
   nrfx_qspi_config_t config = NRFX_QSPI_DEFAULT_CONFIG(
       dev->qspi->clk_gpio, dev->qspi->cs_gpio, dev->qspi->data_gpio[0], dev->qspi->data_gpio[1],
       dev->qspi->data_gpio[2], dev->qspi->data_gpio[3]);
-  config.phy_if.sck_freq = NRF_QSPI_FREQ_32MDIV1;
+  config.phy_if.sck_freq = NRF_QSPI_FREQ_32MDIV4;
 
   switch (dev->read_mode) {
     case QSPI_FLASH_READ_READ2O: