0007-ipts.patch 195 KB

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  1. From 5ab23410ddbe3088444af99d1296a4164365fc70 Mon Sep 17 00:00:00 2001
  2. From: Maximilian Luz <luzmaximilian@gmail.com>
  3. Date: Sat, 28 Sep 2019 17:58:17 +0200
  4. Subject: [PATCH 7/8] ipts
  5. ---
  6. drivers/gpu/drm/i915/Makefile | 3 +
  7. drivers/gpu/drm/i915/i915_debugfs.c | 63 +-
  8. drivers/gpu/drm/i915/i915_drv.c | 9 +-
  9. drivers/gpu/drm/i915/i915_drv.h | 3 +
  10. drivers/gpu/drm/i915/i915_gem_context.c | 12 +
  11. drivers/gpu/drm/i915/i915_irq.c | 7 +-
  12. drivers/gpu/drm/i915/i915_params.c | 5 +-
  13. drivers/gpu/drm/i915/i915_params.h | 5 +-
  14. drivers/gpu/drm/i915/intel_guc.h | 1 +
  15. drivers/gpu/drm/i915/intel_guc_submission.c | 89 +-
  16. drivers/gpu/drm/i915/intel_guc_submission.h | 4 +
  17. drivers/gpu/drm/i915/intel_ipts.c | 650 ++++++++++++
  18. drivers/gpu/drm/i915/intel_ipts.h | 34 +
  19. drivers/gpu/drm/i915/intel_lrc.c | 12 +-
  20. drivers/gpu/drm/i915/intel_lrc.h | 8 +
  21. drivers/gpu/drm/i915/intel_panel.c | 7 +
  22. drivers/misc/Kconfig | 1 +
  23. drivers/misc/Makefile | 1 +
  24. drivers/misc/ipts/Kconfig | 12 +
  25. drivers/misc/ipts/Makefile | 19 +
  26. drivers/misc/ipts/companion.c | 211 ++++
  27. drivers/misc/ipts/companion.h | 25 +
  28. drivers/misc/ipts/companion/Kconfig | 8 +
  29. drivers/misc/ipts/companion/Makefile | 2 +
  30. drivers/misc/ipts/companion/ipts-surface.c | 157 +++
  31. drivers/misc/ipts/dbgfs.c | 277 +++++
  32. drivers/misc/ipts/gfx.c | 180 ++++
  33. drivers/misc/ipts/gfx.h | 25 +
  34. drivers/misc/ipts/hid.c | 469 +++++++++
  35. drivers/misc/ipts/hid.h | 21 +
  36. drivers/misc/ipts/ipts.c | 62 ++
  37. drivers/misc/ipts/ipts.h | 172 +++
  38. drivers/misc/ipts/kernel.c | 1047 +++++++++++++++++++
  39. drivers/misc/ipts/kernel.h | 17 +
  40. drivers/misc/ipts/mei-msgs.h | 901 ++++++++++++++++
  41. drivers/misc/ipts/mei.c | 238 +++++
  42. drivers/misc/ipts/msg-handler.c | 405 +++++++
  43. drivers/misc/ipts/msg-handler.h | 28 +
  44. drivers/misc/ipts/params.c | 42 +
  45. drivers/misc/ipts/params.h | 25 +
  46. drivers/misc/ipts/resource.c | 291 ++++++
  47. drivers/misc/ipts/resource.h | 26 +
  48. drivers/misc/ipts/sensor-regs.h | 834 +++++++++++++++
  49. drivers/misc/ipts/state.h | 22 +
  50. drivers/misc/mei/hw-me-regs.h | 1 +
  51. drivers/misc/mei/pci-me.c | 1 +
  52. include/linux/ipts-binary.h | 140 +++
  53. include/linux/ipts-companion.h | 29 +
  54. include/linux/ipts-gfx.h | 86 ++
  55. include/linux/ipts.h | 19 +
  56. 50 files changed, 6684 insertions(+), 22 deletions(-)
  57. create mode 100644 drivers/gpu/drm/i915/intel_ipts.c
  58. create mode 100644 drivers/gpu/drm/i915/intel_ipts.h
  59. create mode 100644 drivers/misc/ipts/Kconfig
  60. create mode 100644 drivers/misc/ipts/Makefile
  61. create mode 100644 drivers/misc/ipts/companion.c
  62. create mode 100644 drivers/misc/ipts/companion.h
  63. create mode 100644 drivers/misc/ipts/companion/Kconfig
  64. create mode 100644 drivers/misc/ipts/companion/Makefile
  65. create mode 100644 drivers/misc/ipts/companion/ipts-surface.c
  66. create mode 100644 drivers/misc/ipts/dbgfs.c
  67. create mode 100644 drivers/misc/ipts/gfx.c
  68. create mode 100644 drivers/misc/ipts/gfx.h
  69. create mode 100644 drivers/misc/ipts/hid.c
  70. create mode 100644 drivers/misc/ipts/hid.h
  71. create mode 100644 drivers/misc/ipts/ipts.c
  72. create mode 100644 drivers/misc/ipts/ipts.h
  73. create mode 100644 drivers/misc/ipts/kernel.c
  74. create mode 100644 drivers/misc/ipts/kernel.h
  75. create mode 100644 drivers/misc/ipts/mei-msgs.h
  76. create mode 100644 drivers/misc/ipts/mei.c
  77. create mode 100644 drivers/misc/ipts/msg-handler.c
  78. create mode 100644 drivers/misc/ipts/msg-handler.h
  79. create mode 100644 drivers/misc/ipts/params.c
  80. create mode 100644 drivers/misc/ipts/params.h
  81. create mode 100644 drivers/misc/ipts/resource.c
  82. create mode 100644 drivers/misc/ipts/resource.h
  83. create mode 100644 drivers/misc/ipts/sensor-regs.h
  84. create mode 100644 drivers/misc/ipts/state.h
  85. create mode 100644 include/linux/ipts-binary.h
  86. create mode 100644 include/linux/ipts-companion.h
  87. create mode 100644 include/linux/ipts-gfx.h
  88. create mode 100644 include/linux/ipts.h
  89. diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
  90. index 5794f102f9b8f..6ae0e91a213af 100644
  91. --- a/drivers/gpu/drm/i915/Makefile
  92. +++ b/drivers/gpu/drm/i915/Makefile
  93. @@ -155,6 +155,9 @@ i915-y += dvo_ch7017.o \
  94. vlv_dsi.o \
  95. vlv_dsi_pll.o
  96. +# intel precise touch & stylus
  97. +i915-y += intel_ipts.o
  98. +
  99. # Post-mortem debug and GPU hang state capture
  100. i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
  101. i915-$(CONFIG_DRM_I915_SELFTEST) += \
  102. diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
  103. index e063e98d1e82e..99becb6aed688 100644
  104. --- a/drivers/gpu/drm/i915/i915_debugfs.c
  105. +++ b/drivers/gpu/drm/i915/i915_debugfs.c
  106. @@ -31,6 +31,7 @@
  107. #include <linux/sched/mm.h>
  108. #include "intel_drv.h"
  109. #include "intel_guc_submission.h"
  110. +#include "intel_ipts.h"
  111. static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  112. {
  113. @@ -4695,6 +4696,64 @@ static const struct file_operations i915_fifo_underrun_reset_ops = {
  114. .llseek = default_llseek,
  115. };
  116. +static ssize_t
  117. +i915_ipts_cleanup_write(struct file *filp,
  118. + const char __user *ubuf,
  119. + size_t cnt, loff_t *ppos)
  120. +{
  121. + struct drm_i915_private *dev_priv = filp->private_data;
  122. + struct drm_device *dev = &dev_priv->drm;
  123. + int ret;
  124. + bool flag;
  125. +
  126. + ret = kstrtobool_from_user(ubuf, cnt, &flag);
  127. + if (ret)
  128. + return ret;
  129. +
  130. + if (!flag)
  131. + return cnt;
  132. +
  133. + ipts_cleanup(dev);
  134. +
  135. + return cnt;
  136. +}
  137. +
  138. +static const struct file_operations i915_ipts_cleanup_ops = {
  139. + .owner = THIS_MODULE,
  140. + .open = simple_open,
  141. + .write = i915_ipts_cleanup_write,
  142. + .llseek = default_llseek,
  143. +};
  144. +
  145. +static ssize_t
  146. +i915_ipts_init_write(struct file *filp,
  147. + const char __user *ubuf,
  148. + size_t cnt, loff_t *ppos)
  149. +{
  150. + struct drm_i915_private *dev_priv = filp->private_data;
  151. + struct drm_device *dev = &dev_priv->drm;
  152. + int ret;
  153. + bool flag;
  154. +
  155. + ret = kstrtobool_from_user(ubuf, cnt, &flag);
  156. + if (ret)
  157. + return ret;
  158. +
  159. + if (!flag)
  160. + return cnt;
  161. +
  162. + ipts_init(dev);
  163. +
  164. + return cnt;
  165. +}
  166. +
  167. +static const struct file_operations i915_ipts_init_ops = {
  168. + .owner = THIS_MODULE,
  169. + .open = simple_open,
  170. + .write = i915_ipts_init_write,
  171. + .llseek = default_llseek,
  172. +};
  173. +
  174. static const struct drm_info_list i915_debugfs_list[] = {
  175. {"i915_capabilities", i915_capabilities, 0},
  176. {"i915_gem_objects", i915_gem_object_info, 0},
  177. @@ -4773,7 +4832,9 @@ static const struct i915_debugfs_files {
  178. {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
  179. {"i915_ipc_status", &i915_ipc_status_fops},
  180. {"i915_drrs_ctl", &i915_drrs_ctl_fops},
  181. - {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}
  182. + {"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
  183. + {"i915_ipts_cleanup", &i915_ipts_cleanup_ops},
  184. + {"i915_ipts_init", &i915_ipts_init_ops},
  185. };
  186. int i915_debugfs_register(struct drm_i915_private *dev_priv)
  187. diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
  188. index b0d76a7a0946f..81fba8e5ab050 100644
  189. --- a/drivers/gpu/drm/i915/i915_drv.c
  190. +++ b/drivers/gpu/drm/i915/i915_drv.c
  191. @@ -47,11 +47,12 @@
  192. #include <drm/i915_drm.h>
  193. #include "i915_drv.h"
  194. -#include "i915_trace.h"
  195. #include "i915_pmu.h"
  196. #include "i915_query.h"
  197. +#include "i915_trace.h"
  198. #include "i915_vgpu.h"
  199. #include "intel_drv.h"
  200. +#include "intel_ipts.h"
  201. #include "intel_uc.h"
  202. static struct drm_driver driver;
  203. @@ -696,6 +697,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
  204. /* Only enable hotplug handling once the fbdev is fully set up. */
  205. intel_hpd_init(dev_priv);
  206. + if (INTEL_GEN(dev_priv) >= 9 && i915_modparams.enable_guc && i915_modparams.enable_ipts)
  207. + ipts_init(dev);
  208. +
  209. return 0;
  210. cleanup_gem:
  211. @@ -1438,6 +1442,9 @@ void i915_driver_unload(struct drm_device *dev)
  212. struct drm_i915_private *dev_priv = to_i915(dev);
  213. struct pci_dev *pdev = dev_priv->drm.pdev;
  214. + if (INTEL_GEN(dev_priv) >= 9 && i915_modparams.enable_guc && i915_modparams.enable_ipts)
  215. + ipts_cleanup(dev);
  216. +
  217. i915_driver_unregister(dev_priv);
  218. if (i915_gem_suspend(dev_priv))
  219. diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
  220. index db2e9af49ae6f..99bc0c92c4111 100644
  221. --- a/drivers/gpu/drm/i915/i915_drv.h
  222. +++ b/drivers/gpu/drm/i915/i915_drv.h
  223. @@ -3232,6 +3232,9 @@ void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
  224. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
  225. struct sg_table *pages);
  226. +struct i915_gem_context *
  227. +i915_gem_context_create_ipts(struct drm_device *dev);
  228. +
  229. static inline struct i915_gem_context *
  230. __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
  231. {
  232. diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
  233. index ef383fd429885..89da4ff094312 100644
  234. --- a/drivers/gpu/drm/i915/i915_gem_context.c
  235. +++ b/drivers/gpu/drm/i915/i915_gem_context.c
  236. @@ -472,6 +472,18 @@ static bool needs_preempt_context(struct drm_i915_private *i915)
  237. return HAS_LOGICAL_RING_PREEMPTION(i915);
  238. }
  239. +struct i915_gem_context *i915_gem_context_create_ipts(struct drm_device *dev)
  240. +{
  241. + struct drm_i915_private *dev_priv = to_i915(dev);
  242. + struct i915_gem_context *ctx;
  243. +
  244. + BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  245. +
  246. + ctx = i915_gem_create_context(dev_priv, NULL);
  247. +
  248. + return ctx;
  249. +}
  250. +
  251. int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
  252. {
  253. struct i915_gem_context *ctx;
  254. diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
  255. index b7c3982321369..adf168aed2fe3 100644
  256. --- a/drivers/gpu/drm/i915/i915_irq.c
  257. +++ b/drivers/gpu/drm/i915/i915_irq.c
  258. @@ -36,6 +36,7 @@
  259. #include "i915_drv.h"
  260. #include "i915_trace.h"
  261. #include "intel_drv.h"
  262. +#include "intel_ipts.h"
  263. /**
  264. * DOC: interrupt handling
  265. @@ -1503,6 +1504,9 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
  266. tasklet |= USES_GUC_SUBMISSION(engine->i915);
  267. }
  268. + if (iir & GT_RENDER_PIPECTL_NOTIFY_INTERRUPT && i915_modparams.enable_ipts)
  269. + ipts_notify_complete();
  270. +
  271. if (tasklet)
  272. tasklet_hi_schedule(&engine->execlists.tasklet);
  273. }
  274. @@ -4123,7 +4127,8 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
  275. {
  276. /* These are interrupts we'll toggle with the ring mask register */
  277. uint32_t gt_interrupts[] = {
  278. - GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
  279. + GT_RENDER_PIPECTL_NOTIFY_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
  280. + GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
  281. GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
  282. GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
  283. GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
  284. diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
  285. index 295e981e4a398..84415814c0070 100644
  286. --- a/drivers/gpu/drm/i915/i915_params.c
  287. +++ b/drivers/gpu/drm/i915/i915_params.c
  288. @@ -145,7 +145,10 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
  289. i915_param_named_unsafe(enable_guc, int, 0400,
  290. "Enable GuC load for GuC submission and/or HuC load. "
  291. "Required functionality can be selected using bitmask values. "
  292. - "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
  293. + "(-1=auto [default], 0=disable, 1=GuC submission, 2=HuC load)");
  294. +
  295. +i915_param_named_unsafe(enable_ipts, int, 0400,
  296. + "Enable IPTS Touchscreen and Pen support (default: 1)");
  297. i915_param_named(guc_log_level, int, 0400,
  298. "GuC firmware logging level. Requires GuC to be loaded. "
  299. diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
  300. index 6c4d4a21474b5..4ab800c3de6d0 100644
  301. --- a/drivers/gpu/drm/i915/i915_params.h
  302. +++ b/drivers/gpu/drm/i915/i915_params.h
  303. @@ -46,7 +46,7 @@ struct drm_printer;
  304. param(int, disable_power_well, -1) \
  305. param(int, enable_ips, 1) \
  306. param(int, invert_brightness, 0) \
  307. - param(int, enable_guc, 0) \
  308. + param(int, enable_guc, -1) \
  309. param(int, guc_log_level, -1) \
  310. param(char *, guc_firmware_path, NULL) \
  311. param(char *, huc_firmware_path, NULL) \
  312. @@ -68,7 +68,8 @@ struct drm_printer;
  313. param(bool, nuclear_pageflip, false) \
  314. param(bool, enable_dp_mst, true) \
  315. param(bool, enable_dpcd_backlight, false) \
  316. - param(bool, enable_gvt, false)
  317. + param(bool, enable_gvt, false) \
  318. + param(int, enable_ipts, 1)
  319. #define MEMBER(T, member, ...) T member;
  320. struct i915_params {
  321. diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
  322. index 4121928a495e0..8967376accf30 100644
  323. --- a/drivers/gpu/drm/i915/intel_guc.h
  324. +++ b/drivers/gpu/drm/i915/intel_guc.h
  325. @@ -69,6 +69,7 @@ struct intel_guc {
  326. struct intel_guc_client *execbuf_client;
  327. struct intel_guc_client *preempt_client;
  328. + struct intel_guc_client *ipts_client;
  329. struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
  330. struct workqueue_struct *preempt_wq;
  331. diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
  332. index 4aa5e6463e7b7..da80c5f17feea 100644
  333. --- a/drivers/gpu/drm/i915/intel_guc_submission.c
  334. +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
  335. @@ -88,12 +88,17 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb)
  336. static inline bool is_high_priority(struct intel_guc_client *client)
  337. {
  338. - return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
  339. - client->priority == GUC_CLIENT_PRIORITY_HIGH);
  340. + return (client->priority == GUC_CLIENT_PRIORITY_HIGH);
  341. +}
  342. +
  343. +static inline bool is_high_priority_kmd(struct intel_guc_client *client)
  344. +{
  345. + return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH);
  346. }
  347. static int reserve_doorbell(struct intel_guc_client *client)
  348. {
  349. + struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
  350. unsigned long offset;
  351. unsigned long end;
  352. u16 id;
  353. @@ -106,10 +111,14 @@ static int reserve_doorbell(struct intel_guc_client *client)
  354. * priority contexts, the second half for high-priority ones.
  355. */
  356. offset = 0;
  357. - end = GUC_NUM_DOORBELLS / 2;
  358. - if (is_high_priority(client)) {
  359. - offset = end;
  360. - end += offset;
  361. + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
  362. + end = GUC_NUM_DOORBELLS;
  363. + } else {
  364. + end = GUC_NUM_DOORBELLS/2;
  365. + if (is_high_priority(client)) {
  366. + offset = end;
  367. + end += offset;
  368. + }
  369. }
  370. id = find_next_zero_bit(client->guc->doorbell_bitmap, end, offset);
  371. @@ -355,9 +364,15 @@ static void guc_stage_desc_init(struct intel_guc *guc,
  372. desc = __get_stage_desc(client);
  373. memset(desc, 0, sizeof(*desc));
  374. - desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE |
  375. - GUC_STAGE_DESC_ATTR_KERNEL;
  376. - if (is_high_priority(client))
  377. + desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE;
  378. + if ((client->priority == GUC_CLIENT_PRIORITY_KMD_NORMAL) ||
  379. + (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH)) {
  380. + desc->attribute |= GUC_STAGE_DESC_ATTR_KERNEL;
  381. + } else {
  382. + desc->attribute |= GUC_STAGE_DESC_ATTR_PCH;
  383. + }
  384. +
  385. + if (is_high_priority_kmd(client))
  386. desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT;
  387. desc->stage_id = client->stage_id;
  388. desc->priority = client->priority;
  389. @@ -1204,7 +1219,8 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
  390. I915_WRITE(RING_MODE_GEN7(engine), irqs);
  391. /* route USER_INTERRUPT to Host, all others are sent to GuC. */
  392. - irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
  393. + irqs = (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)
  394. + << GEN8_RCS_IRQ_SHIFT |
  395. GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
  396. /* These three registers have the same bit definitions */
  397. I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
  398. @@ -1349,6 +1365,59 @@ void intel_guc_submission_disable(struct intel_guc *guc)
  399. guc_clients_doorbell_fini(guc);
  400. }
  401. +int i915_guc_ipts_submission_enable(struct drm_i915_private *dev_priv,
  402. + struct i915_gem_context *ctx)
  403. +{
  404. + struct intel_guc *guc = &dev_priv->guc;
  405. + struct intel_guc_client *client;
  406. + int err;
  407. + int ret;
  408. +
  409. + /* client for execbuf submission */
  410. + client = guc_client_alloc(dev_priv,
  411. + INTEL_INFO(dev_priv)->ring_mask,
  412. + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? GUC_CLIENT_PRIORITY_HIGH : GUC_CLIENT_PRIORITY_NORMAL,
  413. + ctx);
  414. + if (IS_ERR(client)) {
  415. + DRM_ERROR("Failed to create normal GuC client!\n");
  416. + return -ENOMEM;
  417. + }
  418. +
  419. + guc->ipts_client = client;
  420. +
  421. + err = intel_guc_sample_forcewake(guc);
  422. + if (err)
  423. + return err;
  424. +
  425. + ret = create_doorbell(guc->ipts_client);
  426. + if (ret)
  427. + return ret;
  428. +
  429. + return 0;
  430. +}
  431. +
  432. +void i915_guc_ipts_submission_disable(struct drm_i915_private *dev_priv)
  433. +{
  434. + struct intel_guc *guc = &dev_priv->guc;
  435. +
  436. + if (!guc->ipts_client)
  437. + return;
  438. +
  439. + destroy_doorbell(guc->ipts_client);
  440. + guc_client_free(guc->ipts_client);
  441. + guc->ipts_client = NULL;
  442. +}
  443. +
  444. +void i915_guc_ipts_reacquire_doorbell(struct drm_i915_private *dev_priv)
  445. +{
  446. + struct intel_guc *guc = &dev_priv->guc;
  447. +
  448. + int err = __guc_allocate_doorbell(guc, guc->ipts_client->stage_id);
  449. +
  450. + if (err)
  451. + DRM_ERROR("Not able to reacquire IPTS doorbell\n");
  452. +}
  453. +
  454. #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
  455. #include "selftests/intel_guc.c"
  456. #endif
  457. diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h b/drivers/gpu/drm/i915/intel_guc_submission.h
  458. index fb081cefef935..71fc7986585ab 100644
  459. --- a/drivers/gpu/drm/i915/intel_guc_submission.h
  460. +++ b/drivers/gpu/drm/i915/intel_guc_submission.h
  461. @@ -79,5 +79,9 @@ void intel_guc_submission_disable(struct intel_guc *guc);
  462. void intel_guc_submission_fini(struct intel_guc *guc);
  463. int intel_guc_preempt_work_create(struct intel_guc *guc);
  464. void intel_guc_preempt_work_destroy(struct intel_guc *guc);
  465. +int i915_guc_ipts_submission_enable(struct drm_i915_private *dev_priv,
  466. + struct i915_gem_context *ctx);
  467. +void i915_guc_ipts_submission_disable(struct drm_i915_private *dev_priv);
  468. +void i915_guc_ipts_reacquire_doorbell(struct drm_i915_private *dev_priv);
  469. #endif
  470. diff --git a/drivers/gpu/drm/i915/intel_ipts.c b/drivers/gpu/drm/i915/intel_ipts.c
  471. new file mode 100644
  472. index 0000000000000..c1199074924a0
  473. --- /dev/null
  474. +++ b/drivers/gpu/drm/i915/intel_ipts.c
  475. @@ -0,0 +1,650 @@
  476. +/*
  477. + * Copyright 2016 Intel Corporation
  478. + *
  479. + * Permission is hereby granted, free of charge, to any person obtaining a
  480. + * copy of this software and associated documentation files (the "Software"),
  481. + * to deal in the Software without restriction, including without limitation
  482. + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  483. + * and/or sell copies of the Software, and to permit persons to whom the
  484. + * Software is furnished to do so, subject to the following conditions:
  485. + *
  486. + * The above copyright notice and this permission notice (including the next
  487. + * paragraph) shall be included in all copies or substantial portions of the
  488. + * Software.
  489. + *
  490. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  491. + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  492. + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  493. + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  494. + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  495. + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  496. + * IN THE SOFTWARE.
  497. + *
  498. + */
  499. +
  500. +#include <drm/drmP.h>
  501. +#include <linux/ipts-gfx.h>
  502. +#include <linux/kernel.h>
  503. +#include <linux/module.h>
  504. +#include <linux/types.h>
  505. +
  506. +#include "intel_guc_submission.h"
  507. +#include "i915_drv.h"
  508. +
  509. +#define SUPPORTED_IPTS_INTERFACE_VERSION 1
  510. +
  511. +#define REACQUIRE_DB_THRESHOLD 10
  512. +
  513. +#define DB_LOST_CHECK_STEP1_INTERVAL 2500 // ms
  514. +#define DB_LOST_CHECK_STEP2_INTERVAL 1000 // ms
  515. +
  516. +// CTX for ipts support
  517. +struct ipts {
  518. + struct drm_device *dev;
  519. + struct i915_gem_context *ipts_context;
  520. + struct ipts_callback ipts_clbks;
  521. +
  522. + // buffers' list
  523. + struct {
  524. + spinlock_t lock;
  525. + struct list_head list;
  526. + } buffers;
  527. +
  528. + void *data;
  529. +
  530. + struct delayed_work reacquire_db_work;
  531. + struct ipts_wq_info wq_info;
  532. + u32 old_tail;
  533. + u32 old_head;
  534. + bool need_reacquire_db;
  535. +
  536. + bool connected;
  537. + bool initialized;
  538. +};
  539. +
  540. +struct ipts ipts;
  541. +
  542. +struct ipts_object {
  543. + struct list_head list;
  544. + struct drm_i915_gem_object *gem_obj;
  545. + void *cpu_addr;
  546. +};
  547. +
  548. +static struct ipts_object *ipts_object_create(size_t size, u32 flags)
  549. +{
  550. + struct drm_i915_private *dev_priv = to_i915(ipts.dev);
  551. + struct ipts_object *obj = NULL;
  552. + struct drm_i915_gem_object *gem_obj = NULL;
  553. + int ret = 0;
  554. +
  555. + obj = kzalloc(sizeof(*obj), GFP_KERNEL);
  556. + if (!obj)
  557. + return NULL;
  558. +
  559. + size = roundup(size, PAGE_SIZE);
  560. + if (size == 0) {
  561. + ret = -EINVAL;
  562. + goto err_out;
  563. + }
  564. +
  565. + // Allocate the new object
  566. + gem_obj = i915_gem_object_create(dev_priv, size);
  567. + if (gem_obj == NULL) {
  568. + ret = -ENOMEM;
  569. + goto err_out;
  570. + }
  571. +
  572. + if (flags & IPTS_BUF_FLAG_CONTIGUOUS) {
  573. + ret = i915_gem_object_attach_phys(gem_obj, PAGE_SIZE);
  574. + if (ret) {
  575. + pr_info(">> ipts no contiguous : %d\n", ret);
  576. + goto err_out;
  577. + }
  578. + }
  579. +
  580. + obj->gem_obj = gem_obj;
  581. +
  582. + spin_lock(&ipts.buffers.lock);
  583. + list_add_tail(&obj->list, &ipts.buffers.list);
  584. + spin_unlock(&ipts.buffers.lock);
  585. +
  586. + return obj;
  587. +
  588. +err_out:
  589. +
  590. + if (gem_obj)
  591. + i915_gem_free_object(&gem_obj->base);
  592. +
  593. + kfree(obj);
  594. +
  595. + return NULL;
  596. +}
  597. +
  598. +static void ipts_object_free(struct ipts_object *obj)
  599. +{
  600. + spin_lock(&ipts.buffers.lock);
  601. + list_del(&obj->list);
  602. + spin_unlock(&ipts.buffers.lock);
  603. +
  604. + i915_gem_free_object(&obj->gem_obj->base);
  605. + kfree(obj);
  606. +}
  607. +
  608. +static int ipts_object_pin(struct ipts_object *obj,
  609. + struct i915_gem_context *ipts_ctx)
  610. +{
  611. + struct i915_address_space *vm = NULL;
  612. + struct i915_vma *vma = NULL;
  613. + struct drm_i915_private *dev_priv = to_i915(ipts.dev);
  614. + int ret = 0;
  615. +
  616. + if (ipts_ctx->ppgtt)
  617. + vm = &ipts_ctx->ppgtt->vm;
  618. + else
  619. + vm = &dev_priv->ggtt.vm;
  620. +
  621. + vma = i915_vma_instance(obj->gem_obj, vm, NULL);
  622. + if (IS_ERR(vma)) {
  623. + DRM_ERROR("cannot find or create vma\n");
  624. + return -1;
  625. + }
  626. +
  627. + ret = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_USER);
  628. +
  629. + return ret;
  630. +}
  631. +
  632. +static void ipts_object_unpin(struct ipts_object *obj)
  633. +{
  634. + // TODO: Add support
  635. +}
  636. +
  637. +static void *ipts_object_map(struct ipts_object *obj)
  638. +{
  639. + return i915_gem_object_pin_map(obj->gem_obj, I915_MAP_WB);
  640. +}
  641. +
  642. +static void ipts_object_unmap(struct ipts_object *obj)
  643. +{
  644. + i915_gem_object_unpin_map(obj->gem_obj);
  645. + obj->cpu_addr = NULL;
  646. +}
  647. +
  648. +static int create_ipts_context(void)
  649. +{
  650. + struct i915_gem_context *ipts_ctx = NULL;
  651. + struct drm_i915_private *dev_priv = to_i915(ipts.dev);
  652. + struct intel_context *ce = NULL;
  653. + struct intel_context *pin_ret;
  654. + int ret = 0;
  655. +
  656. + // Initialize the context right away.
  657. + ret = i915_mutex_lock_interruptible(ipts.dev);
  658. + if (ret) {
  659. + DRM_ERROR("i915_mutex_lock_interruptible failed\n");
  660. + return ret;
  661. + }
  662. +
  663. + ipts_ctx = i915_gem_context_create_ipts(ipts.dev);
  664. + if (IS_ERR(ipts_ctx)) {
  665. + DRM_ERROR("Failed to create IPTS context (error %ld)\n",
  666. + PTR_ERR(ipts_ctx));
  667. + ret = PTR_ERR(ipts_ctx);
  668. + goto err_unlock;
  669. + }
  670. +
  671. + ce = to_intel_context(ipts_ctx, dev_priv->engine[RCS]);
  672. + if (IS_ERR(ce)) {
  673. + DRM_ERROR("Failed to create intel context (error %ld)\n",
  674. + PTR_ERR(ce));
  675. + ret = PTR_ERR(ce);
  676. + goto err_unlock;
  677. + }
  678. +
  679. + ret = execlists_context_deferred_alloc(ipts_ctx, dev_priv->engine[RCS], ce);
  680. + if (ret) {
  681. + DRM_DEBUG("lr context allocation failed: %d\n", ret);
  682. + goto err_ctx;
  683. + }
  684. +
  685. + pin_ret = execlists_context_pin(dev_priv->engine[RCS], ipts_ctx);
  686. + if (IS_ERR(pin_ret)) {
  687. + DRM_DEBUG("lr context pinning failed: %ld\n", PTR_ERR(pin_ret));
  688. + goto err_ctx;
  689. + }
  690. +
  691. + // Release the mutex
  692. + mutex_unlock(&ipts.dev->struct_mutex);
  693. +
  694. + spin_lock_init(&ipts.buffers.lock);
  695. + INIT_LIST_HEAD(&ipts.buffers.list);
  696. +
  697. + ipts.ipts_context = ipts_ctx;
  698. +
  699. + return 0;
  700. +
  701. +err_ctx:
  702. + if (ipts_ctx)
  703. + i915_gem_context_put(ipts_ctx);
  704. +
  705. +err_unlock:
  706. + mutex_unlock(&ipts.dev->struct_mutex);
  707. +
  708. + return ret;
  709. +}
  710. +
  711. +static void destroy_ipts_context(void)
  712. +{
  713. + struct i915_gem_context *ipts_ctx = NULL;
  714. + struct drm_i915_private *dev_priv = to_i915(ipts.dev);
  715. + struct intel_context *ce = NULL;
  716. + int ret = 0;
  717. +
  718. + ipts_ctx = ipts.ipts_context;
  719. +
  720. + ce = to_intel_context(ipts_ctx, dev_priv->engine[RCS]);
  721. +
  722. + // Initialize the context right away.
  723. + ret = i915_mutex_lock_interruptible(ipts.dev);
  724. + if (ret) {
  725. + DRM_ERROR("i915_mutex_lock_interruptible failed\n");
  726. + return;
  727. + }
  728. +
  729. + execlists_context_unpin(ce);
  730. + i915_gem_context_put(ipts_ctx);
  731. +
  732. + mutex_unlock(&ipts.dev->struct_mutex);
  733. +}
  734. +
  735. +int ipts_notify_complete(void)
  736. +{
  737. + if (ipts.ipts_clbks.workload_complete)
  738. + ipts.ipts_clbks.workload_complete(ipts.data);
  739. +
  740. + return 0;
  741. +}
  742. +
  743. +int ipts_notify_backlight_status(bool backlight_on)
  744. +{
  745. + if (ipts.ipts_clbks.notify_gfx_status) {
  746. + if (backlight_on) {
  747. + ipts.ipts_clbks.notify_gfx_status(
  748. + IPTS_NOTIFY_STA_BACKLIGHT_ON, ipts.data);
  749. + schedule_delayed_work(&ipts.reacquire_db_work,
  750. + msecs_to_jiffies(DB_LOST_CHECK_STEP1_INTERVAL));
  751. + } else {
  752. + ipts.ipts_clbks.notify_gfx_status(
  753. + IPTS_NOTIFY_STA_BACKLIGHT_OFF, ipts.data);
  754. + cancel_delayed_work(&ipts.reacquire_db_work);
  755. + }
  756. + }
  757. +
  758. + return 0;
  759. +}
  760. +
  761. +static void ipts_reacquire_db(struct ipts *ipts_p)
  762. +{
  763. + int ret = 0;
  764. +
  765. + ret = i915_mutex_lock_interruptible(ipts_p->dev);
  766. + if (ret) {
  767. + DRM_ERROR("i915_mutex_lock_interruptible failed\n");
  768. + return;
  769. + }
  770. +
  771. + // Reacquire the doorbell
  772. + i915_guc_ipts_reacquire_doorbell(ipts_p->dev->dev_private);
  773. +
  774. + mutex_unlock(&ipts_p->dev->struct_mutex);
  775. +}
  776. +
  777. +static int ipts_get_wq_info(uint64_t gfx_handle,
  778. + struct ipts_wq_info *wq_info)
  779. +{
  780. + if (gfx_handle != (uint64_t)&ipts) {
  781. + DRM_ERROR("invalid gfx handle\n");
  782. + return -EINVAL;
  783. + }
  784. +
  785. + *wq_info = ipts.wq_info;
  786. +
  787. + ipts_reacquire_db(&ipts);
  788. + schedule_delayed_work(&ipts.reacquire_db_work,
  789. + msecs_to_jiffies(DB_LOST_CHECK_STEP1_INTERVAL));
  790. +
  791. + return 0;
  792. +}
  793. +
  794. +static int set_wq_info(void)
  795. +{
  796. + struct drm_i915_private *dev_priv = to_i915(ipts.dev);
  797. + struct intel_guc *guc = &dev_priv->guc;
  798. + struct intel_guc_client *client;
  799. + struct guc_process_desc *desc;
  800. + struct ipts_wq_info *wq_info;
  801. + void *base = NULL;
  802. + u64 phy_base = 0;
  803. +
  804. + wq_info = &ipts.wq_info;
  805. +
  806. + client = guc->ipts_client;
  807. + if (!client) {
  808. + DRM_ERROR("IPTS GuC client is NOT available\n");
  809. + return -EINVAL;
  810. + }
  811. +
  812. + base = client->vaddr;
  813. + desc = (struct guc_process_desc *)
  814. + ((u64)base + client->proc_desc_offset);
  815. +
  816. + desc->wq_base_addr = (u64)base + GUC_DB_SIZE;
  817. + desc->db_base_addr = (u64)base + client->doorbell_offset;
  818. +
  819. + // IPTS expects physical addresses to pass it to ME
  820. + phy_base = sg_dma_address(client->vma->pages->sgl);
  821. +
  822. + wq_info->db_addr = desc->db_base_addr;
  823. + wq_info->db_phy_addr = phy_base + client->doorbell_offset;
  824. + wq_info->db_cookie_offset = offsetof(struct guc_doorbell_info, cookie);
  825. + wq_info->wq_addr = desc->wq_base_addr;
  826. + wq_info->wq_phy_addr = phy_base + GUC_DB_SIZE;
  827. + wq_info->wq_head_addr = (u64)&desc->head;
  828. + wq_info->wq_tail_addr = (u64)&desc->tail;
  829. + wq_info->wq_size = desc->wq_size_bytes;
  830. +
  831. + wq_info->wq_head_phy_addr = phy_base + client->proc_desc_offset +
  832. + offsetof(struct guc_process_desc, head);
  833. +
  834. + wq_info->wq_tail_phy_addr = phy_base + client->proc_desc_offset +
  835. + offsetof(struct guc_process_desc, tail);
  836. +
  837. + return 0;
  838. +}
  839. +
  840. +static int ipts_init_wq(void)
  841. +{
  842. + int ret = 0;
  843. +
  844. + ret = i915_mutex_lock_interruptible(ipts.dev);
  845. + if (ret) {
  846. + DRM_ERROR("i915_mutex_lock_interruptible failed\n");
  847. + return ret;
  848. + }
  849. +
  850. + // disable IPTS submission
  851. + i915_guc_ipts_submission_disable(ipts.dev->dev_private);
  852. +
  853. + // enable IPTS submission
  854. + ret = i915_guc_ipts_submission_enable(ipts.dev->dev_private,
  855. + ipts.ipts_context);
  856. + if (ret) {
  857. + DRM_ERROR("i915_guc_ipts_submission_enable failed: %d\n", ret);
  858. + goto out;
  859. + }
  860. +
  861. + ret = set_wq_info();
  862. + if (ret) {
  863. + DRM_ERROR("set_wq_info failed\n");
  864. + goto out;
  865. + }
  866. +
  867. +out:
  868. + mutex_unlock(&ipts.dev->struct_mutex);
  869. +
  870. + return ret;
  871. +}
  872. +
  873. +static void ipts_release_wq(void)
  874. +{
  875. + int ret = 0;
  876. +
  877. + ret = i915_mutex_lock_interruptible(ipts.dev);
  878. + if (ret) {
  879. + DRM_ERROR("i915_mutex_lock_interruptible failed\n");
  880. + return;
  881. + }
  882. +
  883. + // disable IPTS submission
  884. + i915_guc_ipts_submission_disable(ipts.dev->dev_private);
  885. +
  886. + mutex_unlock(&ipts.dev->struct_mutex);
  887. +}
  888. +
  889. +static int ipts_map_buffer(u64 gfx_handle, struct ipts_mapbuffer *mapbuf)
  890. +{
  891. + struct ipts_object *obj;
  892. + struct i915_gem_context *ipts_ctx = NULL;
  893. + struct drm_i915_private *dev_priv = to_i915(ipts.dev);
  894. + struct i915_address_space *vm = NULL;
  895. + struct i915_vma *vma = NULL;
  896. + int ret = 0;
  897. +
  898. + if (gfx_handle != (uint64_t)&ipts) {
  899. + DRM_ERROR("invalid gfx handle\n");
  900. + return -EINVAL;
  901. + }
  902. +
  903. + // Acquire mutex first
  904. + ret = i915_mutex_lock_interruptible(ipts.dev);
  905. + if (ret) {
  906. + DRM_ERROR("i915_mutex_lock_interruptible failed\n");
  907. + return -EINVAL;
  908. + }
  909. +
  910. + obj = ipts_object_create(mapbuf->size, mapbuf->flags);
  911. + if (!obj)
  912. + return -ENOMEM;
  913. +
  914. + ipts_ctx = ipts.ipts_context;
  915. + ret = ipts_object_pin(obj, ipts_ctx);
  916. + if (ret) {
  917. + DRM_ERROR("Not able to pin iTouch obj\n");
  918. + ipts_object_free(obj);
  919. + mutex_unlock(&ipts.dev->struct_mutex);
  920. + return -ENOMEM;
  921. + }
  922. +
  923. + if (mapbuf->flags & IPTS_BUF_FLAG_CONTIGUOUS)
  924. + obj->cpu_addr = obj->gem_obj->phys_handle->vaddr;
  925. + else
  926. + obj->cpu_addr = ipts_object_map(obj);
  927. +
  928. + if (ipts_ctx->ppgtt)
  929. + vm = &ipts_ctx->ppgtt->vm;
  930. + else
  931. + vm = &dev_priv->ggtt.vm;
  932. +
  933. + vma = i915_vma_instance(obj->gem_obj, vm, NULL);
  934. + if (IS_ERR(vma)) {
  935. + DRM_ERROR("cannot find or create vma\n");
  936. + return -EINVAL;
  937. + }
  938. +
  939. + mapbuf->gfx_addr = (void *)vma->node.start;
  940. + mapbuf->cpu_addr = (void *)obj->cpu_addr;
  941. + mapbuf->buf_handle = (u64)obj;
  942. + if (mapbuf->flags & IPTS_BUF_FLAG_CONTIGUOUS)
  943. + mapbuf->phy_addr = (u64)obj->gem_obj->phys_handle->busaddr;
  944. +
  945. + // Release the mutex
  946. + mutex_unlock(&ipts.dev->struct_mutex);
  947. +
  948. + return 0;
  949. +}
  950. +
  951. +static int ipts_unmap_buffer(uint64_t gfx_handle, uint64_t buf_handle)
  952. +{
  953. + struct ipts_object *obj = (struct ipts_object *)buf_handle;
  954. +
  955. + if (gfx_handle != (uint64_t)&ipts) {
  956. + DRM_ERROR("invalid gfx handle\n");
  957. + return -EINVAL;
  958. + }
  959. +
  960. + if (!obj->gem_obj->phys_handle)
  961. + ipts_object_unmap(obj);
  962. +
  963. + ipts_object_unpin(obj);
  964. + ipts_object_free(obj);
  965. +
  966. + return 0;
  967. +}
  968. +
  969. +int ipts_connect(struct ipts_connect *ipts_connect)
  970. +{
  971. + u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
  972. + struct drm_i915_private *dev_priv = to_i915(ipts.dev);
  973. +
  974. + if (!ipts.initialized)
  975. + return -EIO;
  976. +
  977. + if (!ipts_connect)
  978. + return -EINVAL;
  979. +
  980. + if (ipts_connect->if_version > SUPPORTED_IPTS_INTERFACE_VERSION)
  981. + return -EINVAL;
  982. +
  983. + // set up device-link for PM
  984. + if (!device_link_add(ipts_connect->client, ipts.dev->dev, flags))
  985. + return -EFAULT;
  986. +
  987. + // return gpu operations for ipts
  988. + ipts_connect->ipts_ops.get_wq_info = ipts_get_wq_info;
  989. + ipts_connect->ipts_ops.map_buffer = ipts_map_buffer;
  990. + ipts_connect->ipts_ops.unmap_buffer = ipts_unmap_buffer;
  991. + ipts_connect->gfx_version = INTEL_INFO(dev_priv)->gen;
  992. + ipts_connect->gfx_handle = (uint64_t)&ipts;
  993. +
  994. + // save callback and data
  995. + ipts.data = ipts_connect->data;
  996. + ipts.ipts_clbks = ipts_connect->ipts_cb;
  997. +
  998. + ipts.connected = true;
  999. +
  1000. + return 0;
  1001. +}
  1002. +EXPORT_SYMBOL_GPL(ipts_connect);
  1003. +
  1004. +void ipts_disconnect(uint64_t gfx_handle)
  1005. +{
  1006. + if (!ipts.initialized)
  1007. + return;
  1008. +
  1009. + if (gfx_handle != (uint64_t)&ipts || !ipts.connected) {
  1010. + DRM_ERROR("invalid gfx handle\n");
  1011. + return;
  1012. + }
  1013. +
  1014. + ipts.data = 0;
  1015. + memset(&ipts.ipts_clbks, 0, sizeof(struct ipts_callback));
  1016. +
  1017. + ipts.connected = false;
  1018. +}
  1019. +EXPORT_SYMBOL_GPL(ipts_disconnect);
  1020. +
  1021. +static void reacquire_db_work_func(struct work_struct *work)
  1022. +{
  1023. + struct delayed_work *d_work = container_of(work,
  1024. + struct delayed_work, work);
  1025. + struct ipts *ipts_p = container_of(d_work,
  1026. + struct ipts, reacquire_db_work);
  1027. + u32 head;
  1028. + u32 tail;
  1029. + u32 size;
  1030. + u32 load;
  1031. +
  1032. + head = *(u32 *)ipts_p->wq_info.wq_head_addr;
  1033. + tail = *(u32 *)ipts_p->wq_info.wq_tail_addr;
  1034. + size = ipts_p->wq_info.wq_size;
  1035. +
  1036. + if (head >= tail)
  1037. + load = head - tail;
  1038. + else
  1039. + load = head + size - tail;
  1040. +
  1041. + if (load < REACQUIRE_DB_THRESHOLD) {
  1042. + ipts_p->need_reacquire_db = false;
  1043. + goto reschedule_work;
  1044. + }
  1045. +
  1046. + if (ipts_p->need_reacquire_db) {
  1047. + if (ipts_p->old_head == head &&
  1048. + ipts_p->old_tail == tail)
  1049. + ipts_reacquire_db(ipts_p);
  1050. + ipts_p->need_reacquire_db = false;
  1051. + } else {
  1052. + ipts_p->old_head = head;
  1053. + ipts_p->old_tail = tail;
  1054. + ipts_p->need_reacquire_db = true;
  1055. +
  1056. + // recheck
  1057. + schedule_delayed_work(&ipts_p->reacquire_db_work,
  1058. + msecs_to_jiffies(DB_LOST_CHECK_STEP2_INTERVAL));
  1059. + return;
  1060. + }
  1061. +
  1062. +reschedule_work:
  1063. + schedule_delayed_work(&ipts_p->reacquire_db_work,
  1064. + msecs_to_jiffies(DB_LOST_CHECK_STEP1_INTERVAL));
  1065. +}
  1066. +
  1067. +/**
  1068. + * ipts_init - Initialize ipts support
  1069. + * @dev: drm device
  1070. + *
  1071. + * Setup the required structures for ipts.
  1072. + */
  1073. +int ipts_init(struct drm_device *dev)
  1074. +{
  1075. + int ret = 0;
  1076. +
  1077. + pr_info("ipts: initializing ipts\n");
  1078. +
  1079. + ipts.dev = dev;
  1080. + INIT_DELAYED_WORK(&ipts.reacquire_db_work,
  1081. + reacquire_db_work_func);
  1082. +
  1083. + ret = create_ipts_context();
  1084. + if (ret)
  1085. + return -ENOMEM;
  1086. +
  1087. + ret = ipts_init_wq();
  1088. + if (ret)
  1089. + return ret;
  1090. +
  1091. + ipts.initialized = true;
  1092. + pr_info("ipts: Intel iTouch framework initialized\n");
  1093. +
  1094. + return ret;
  1095. +}
  1096. +
  1097. +void ipts_cleanup(struct drm_device *dev)
  1098. +{
  1099. + struct ipts_object *obj, *n;
  1100. +
  1101. + if (ipts.dev != dev)
  1102. + return;
  1103. +
  1104. + list_for_each_entry_safe(obj, n, &ipts.buffers.list, list) {
  1105. + struct i915_vma *vma, *vn;
  1106. +
  1107. + list_for_each_entry_safe(vma, vn, &obj->list, obj_link) {
  1108. + vma->flags &= ~I915_VMA_PIN_MASK;
  1109. + i915_vma_destroy(vma);
  1110. + }
  1111. +
  1112. + list_del(&obj->list);
  1113. +
  1114. + if (!obj->gem_obj->phys_handle)
  1115. + ipts_object_unmap(obj);
  1116. +
  1117. + ipts_object_unpin(obj);
  1118. + i915_gem_free_object(&obj->gem_obj->base);
  1119. + kfree(obj);
  1120. + }
  1121. +
  1122. + ipts_release_wq();
  1123. + destroy_ipts_context();
  1124. + cancel_delayed_work(&ipts.reacquire_db_work);
  1125. +}
  1126. diff --git a/drivers/gpu/drm/i915/intel_ipts.h b/drivers/gpu/drm/i915/intel_ipts.h
  1127. new file mode 100644
  1128. index 0000000000000..67f90b72f2378
  1129. --- /dev/null
  1130. +++ b/drivers/gpu/drm/i915/intel_ipts.h
  1131. @@ -0,0 +1,34 @@
  1132. +/*
  1133. + * Copyright © 2016 Intel Corporation
  1134. + *
  1135. + * Permission is hereby granted, free of charge, to any person obtaining a
  1136. + * copy of this software and associated documentation files (the "Software"),
  1137. + * to deal in the Software without restriction, including without limitation
  1138. + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  1139. + * and/or sell copies of the Software, and to permit persons to whom the
  1140. + * Software is furnished to do so, subject to the following conditions:
  1141. + *
  1142. + * The above copyright notice and this permission notice (including the next
  1143. + * paragraph) shall be included in all copies or substantial portions of the
  1144. + * Software.
  1145. + *
  1146. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  1147. + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  1148. + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  1149. + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  1150. + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  1151. + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  1152. + * IN THE SOFTWARE.
  1153. + *
  1154. + */
  1155. +#ifndef _INTEL_IPTS_H_
  1156. +#define _INTEL_IPTS_H_
  1157. +
  1158. +#include <drm/drm_device.h>
  1159. +
  1160. +int ipts_init(struct drm_device *dev);
  1161. +void ipts_cleanup(struct drm_device *dev);
  1162. +int ipts_notify_backlight_status(bool backlight_on);
  1163. +int ipts_notify_complete(void);
  1164. +
  1165. +#endif //_INTEL_IPTS_H_
  1166. diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
  1167. index 13e97faabaa74..a4af67d3d6ffd 100644
  1168. --- a/drivers/gpu/drm/i915/intel_lrc.c
  1169. +++ b/drivers/gpu/drm/i915/intel_lrc.c
  1170. @@ -164,9 +164,6 @@
  1171. #define WA_TAIL_DWORDS 2
  1172. #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
  1173. -static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
  1174. - struct intel_engine_cs *engine,
  1175. - struct intel_context *ce);
  1176. static void execlists_init_reg_state(u32 *reg_state,
  1177. struct i915_gem_context *ctx,
  1178. struct intel_engine_cs *engine,
  1179. @@ -1292,7 +1289,7 @@ static void execlists_context_destroy(struct intel_context *ce)
  1180. i915_gem_object_put(ce->state->obj);
  1181. }
  1182. -static void execlists_context_unpin(struct intel_context *ce)
  1183. +void execlists_context_unpin(struct intel_context *ce)
  1184. {
  1185. intel_ring_unpin(ce->ring);
  1186. @@ -1379,7 +1376,7 @@ static const struct intel_context_ops execlists_context_ops = {
  1187. .destroy = execlists_context_destroy,
  1188. };
  1189. -static struct intel_context *
  1190. +struct intel_context *
  1191. execlists_context_pin(struct intel_engine_cs *engine,
  1192. struct i915_gem_context *ctx)
  1193. {
  1194. @@ -2479,6 +2476,9 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
  1195. logical_ring_setup(engine);
  1196. + engine->irq_keep_mask |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
  1197. + << GEN8_RCS_IRQ_SHIFT;
  1198. +
  1199. if (HAS_L3_DPF(dev_priv))
  1200. engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
  1201. @@ -2743,7 +2743,7 @@ populate_lr_context(struct i915_gem_context *ctx,
  1202. return ret;
  1203. }
  1204. -static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
  1205. +int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
  1206. struct intel_engine_cs *engine,
  1207. struct intel_context *ce)
  1208. {
  1209. diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
  1210. index 4dfb78e3ec7e4..32159231a16e7 100644
  1211. --- a/drivers/gpu/drm/i915/intel_lrc.h
  1212. +++ b/drivers/gpu/drm/i915/intel_lrc.h
  1213. @@ -106,4 +106,12 @@ void intel_lr_context_resume(struct drm_i915_private *dev_priv);
  1214. void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
  1215. +struct intel_context *
  1216. +execlists_context_pin(struct intel_engine_cs *engine,
  1217. + struct i915_gem_context *ctx);
  1218. +void execlists_context_unpin(struct intel_context *ce);
  1219. +int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
  1220. + struct intel_engine_cs *engine,
  1221. + struct intel_context *ce);
  1222. +
  1223. #endif /* _INTEL_LRC_H_ */
  1224. diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
  1225. index 4a9f139e7b738..c137a57f67026 100644
  1226. --- a/drivers/gpu/drm/i915/intel_panel.c
  1227. +++ b/drivers/gpu/drm/i915/intel_panel.c
  1228. @@ -34,6 +34,7 @@
  1229. #include <linux/moduleparam.h>
  1230. #include <linux/pwm.h>
  1231. #include "intel_drv.h"
  1232. +#include "intel_ipts.h"
  1233. #define CRC_PMIC_PWM_PERIOD_NS 21333
  1234. @@ -659,6 +660,9 @@ static void lpt_disable_backlight(const struct drm_connector_state *old_conn_sta
  1235. struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
  1236. u32 tmp;
  1237. + if (INTEL_GEN(dev_priv) >= 9 && i915_modparams.enable_guc && i915_modparams.enable_ipts)
  1238. + ipts_notify_backlight_status(false);
  1239. +
  1240. intel_panel_actually_set_backlight(old_conn_state, 0);
  1241. /*
  1242. @@ -846,6 +850,9 @@ static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state,
  1243. /* This won't stick until the above enable. */
  1244. intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
  1245. +
  1246. + if (INTEL_GEN(dev_priv) >= 9 && i915_modparams.enable_guc && i915_modparams.enable_ipts)
  1247. + ipts_notify_backlight_status(true);
  1248. }
  1249. static void pch_enable_backlight(const struct intel_crtc_state *crtc_state,
  1250. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
  1251. index 3726eacdf65de..77263b5f5915a 100644
  1252. --- a/drivers/misc/Kconfig
  1253. +++ b/drivers/misc/Kconfig
  1254. @@ -520,6 +520,7 @@ source "drivers/misc/ti-st/Kconfig"
  1255. source "drivers/misc/lis3lv02d/Kconfig"
  1256. source "drivers/misc/altera-stapl/Kconfig"
  1257. source "drivers/misc/mei/Kconfig"
  1258. +source "drivers/misc/ipts/Kconfig"
  1259. source "drivers/misc/vmw_vmci/Kconfig"
  1260. source "drivers/misc/mic/Kconfig"
  1261. source "drivers/misc/genwqe/Kconfig"
  1262. diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
  1263. index af22bbc3d00cb..eb1eb0d58c327 100644
  1264. --- a/drivers/misc/Makefile
  1265. +++ b/drivers/misc/Makefile
  1266. @@ -44,6 +44,7 @@ obj-y += lis3lv02d/
  1267. obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o
  1268. obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/
  1269. obj-$(CONFIG_INTEL_MEI) += mei/
  1270. +obj-$(CONFIG_INTEL_IPTS) += ipts/
  1271. obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/
  1272. obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o
  1273. obj-$(CONFIG_SRAM) += sram.o
  1274. diff --git a/drivers/misc/ipts/Kconfig b/drivers/misc/ipts/Kconfig
  1275. new file mode 100644
  1276. index 0000000000000..900d2c58ca74c
  1277. --- /dev/null
  1278. +++ b/drivers/misc/ipts/Kconfig
  1279. @@ -0,0 +1,12 @@
  1280. +# SPDX-License-Identifier: GPL-2.0-or-later
  1281. +config INTEL_IPTS
  1282. + tristate "Intel Precise Touch & Stylus"
  1283. + select INTEL_MEI
  1284. + depends on X86 && PCI && HID && DRM_I915
  1285. + help
  1286. + Intel Precise Touch & Stylus support
  1287. + Supported SoCs:
  1288. + Intel Skylake
  1289. + Intel Kabylake
  1290. +
  1291. +source "drivers/misc/ipts/companion/Kconfig"
  1292. diff --git a/drivers/misc/ipts/Makefile b/drivers/misc/ipts/Makefile
  1293. new file mode 100644
  1294. index 0000000000000..bb3982f48afcb
  1295. --- /dev/null
  1296. +++ b/drivers/misc/ipts/Makefile
  1297. @@ -0,0 +1,19 @@
  1298. +# SPDX-License-Identifier: GPL-2.0-or-later
  1299. +#
  1300. +# Makefile - Intel Precise Touch & Stylus device driver
  1301. +# Copyright (c) 2016 Intel Corporation
  1302. +#
  1303. +
  1304. +obj-$(CONFIG_INTEL_IPTS)+= intel-ipts.o
  1305. +intel-ipts-objs += companion.o
  1306. +intel-ipts-objs += ipts.o
  1307. +intel-ipts-objs += mei.o
  1308. +intel-ipts-objs += hid.o
  1309. +intel-ipts-objs += msg-handler.o
  1310. +intel-ipts-objs += kernel.o
  1311. +intel-ipts-objs += params.o
  1312. +intel-ipts-objs += resource.o
  1313. +intel-ipts-objs += gfx.o
  1314. +intel-ipts-$(CONFIG_DEBUG_FS) += dbgfs.o
  1315. +
  1316. +obj-y += companion/
  1317. diff --git a/drivers/misc/ipts/companion.c b/drivers/misc/ipts/companion.c
  1318. new file mode 100644
  1319. index 0000000000000..8f66b852f1371
  1320. --- /dev/null
  1321. +++ b/drivers/misc/ipts/companion.c
  1322. @@ -0,0 +1,211 @@
  1323. +// SPDX-License-Identifier: GPL-2.0-or-later
  1324. +/*
  1325. + *
  1326. + * Intel Precise Touch & Stylus
  1327. + * Copyright (c) 2016 Intel Corporation
  1328. + *
  1329. + */
  1330. +
  1331. +#include <linux/firmware.h>
  1332. +#include <linux/ipts.h>
  1333. +#include <linux/ipts-binary.h>
  1334. +#include <linux/ipts-companion.h>
  1335. +#include <linux/mutex.h>
  1336. +
  1337. +#include "companion.h"
  1338. +#include "ipts.h"
  1339. +#include "params.h"
  1340. +
  1341. +#define IPTS_FW_PATH_FMT "intel/ipts/%s"
  1342. +#define IPTS_FW_CONFIG_FILE "ipts_fw_config.bin"
  1343. +
  1344. +struct ipts_companion *ipts_companion;
  1345. +DEFINE_MUTEX(ipts_companion_lock);
  1346. +
  1347. +bool ipts_companion_available(void)
  1348. +{
  1349. + bool ret;
  1350. +
  1351. + mutex_lock(&ipts_companion_lock);
  1352. +
  1353. + ret = ipts_companion != NULL;
  1354. +
  1355. + mutex_unlock(&ipts_companion_lock);
  1356. +
  1357. + return ret;
  1358. +}
  1359. +
  1360. +/*
  1361. + * General purpose API for adding or removing a companion driver
  1362. + * A companion driver is a driver that implements hardware specific
  1363. + * behaviour into IPTS, so it doesn't have to be hardcoded into the
  1364. + * main driver. All requests to the companion driver should be wrapped,
  1365. + * with a fallback in case a companion driver cannot be found.
  1366. + */
  1367. +
  1368. +int ipts_add_companion(struct ipts_companion *companion)
  1369. +{
  1370. + int ret;
  1371. +
  1372. + // Make sure that access to the companion is synchronized
  1373. + mutex_lock(&ipts_companion_lock);
  1374. +
  1375. + if (ipts_companion == NULL) {
  1376. + ret = 0;
  1377. + ipts_companion = companion;
  1378. + } else {
  1379. + ret = -EBUSY;
  1380. + }
  1381. +
  1382. + mutex_unlock(&ipts_companion_lock);
  1383. +
  1384. + return ret;
  1385. +}
  1386. +EXPORT_SYMBOL_GPL(ipts_add_companion);
  1387. +
  1388. +int ipts_remove_companion(struct ipts_companion *companion)
  1389. +{
  1390. + int ret;
  1391. +
  1392. + // Make sure that access to the companion is synchronized
  1393. + mutex_lock(&ipts_companion_lock);
  1394. +
  1395. + if (ipts_companion != NULL && companion != NULL &&
  1396. + ipts_companion->name != companion->name) {
  1397. + ret = -EPERM;
  1398. + } else {
  1399. + ret = 0;
  1400. + ipts_companion = NULL;
  1401. + }
  1402. +
  1403. + mutex_unlock(&ipts_companion_lock);
  1404. + return ret;
  1405. +}
  1406. +EXPORT_SYMBOL_GPL(ipts_remove_companion);
  1407. +
  1408. +/*
  1409. + * Utility functions for IPTS. These functions replace codepaths in the IPTS
  1410. + * driver, and redirect them to the companion driver, if one was found.
  1411. + * Otherwise the legacy code gets executed as a fallback.
  1412. + */
  1413. +
  1414. +int ipts_request_firmware(const struct firmware **fw, const char *name,
  1415. + struct device *device)
  1416. +{
  1417. + int ret = 0;
  1418. + char fw_path[MAX_IOCL_FILE_PATH_LEN];
  1419. +
  1420. + // Make sure that access to the companion is synchronized
  1421. + mutex_lock(&ipts_companion_lock);
  1422. +
  1423. + // Check if a companion was registered. If not, skip
  1424. + // forward and try to load the firmware from the legacy path
  1425. + if (ipts_companion == NULL || ipts_modparams.ignore_companion)
  1426. + goto request_firmware_fallback;
  1427. +
  1428. + ret = ipts_companion->firmware_request(ipts_companion, fw,
  1429. + name, device);
  1430. + if (!ret)
  1431. + goto request_firmware_return;
  1432. +
  1433. +request_firmware_fallback:
  1434. +
  1435. + // If fallback loading for firmware was disabled, abort.
  1436. + // Return -ENOENT as no firmware file was found.
  1437. + if (ipts_modparams.ignore_fw_fallback) {
  1438. + ret = -ENOENT;
  1439. + goto request_firmware_return;
  1440. + }
  1441. +
  1442. + // No firmware was found by the companion driver, try the generic path.
  1443. + snprintf(fw_path, MAX_IOCL_FILE_PATH_LEN, IPTS_FW_PATH_FMT, name);
  1444. + ret = request_firmware(fw, fw_path, device);
  1445. +
  1446. +request_firmware_return:
  1447. +
  1448. + mutex_unlock(&ipts_companion_lock);
  1449. +
  1450. + return ret;
  1451. +}
  1452. +
  1453. +static struct ipts_bin_fw_list *ipts_alloc_fw_list(
  1454. + struct ipts_bin_fw_info **fw)
  1455. +{
  1456. + int size, len, i, j;
  1457. + struct ipts_bin_fw_list *fw_list;
  1458. + char *itr;
  1459. +
  1460. + // Figure out the amount of firmware files inside of the array
  1461. + len = 0;
  1462. + while (fw[len] != NULL)
  1463. + len++;
  1464. +
  1465. + // Determine the size that the final list will need in memory
  1466. + size = sizeof(struct ipts_bin_fw_list);
  1467. + for (i = 0; i < len; i++) {
  1468. + size += sizeof(struct ipts_bin_fw_info);
  1469. + size += sizeof(struct ipts_bin_data_file_info) *
  1470. + fw[i]->num_of_data_files;
  1471. + }
  1472. +
  1473. + fw_list = kmalloc(size, GFP_KERNEL);
  1474. + fw_list->num_of_fws = len;
  1475. +
  1476. + itr = (char *)fw_list->fw_info;
  1477. + for (i = 0; i < len; i++) {
  1478. + *(struct ipts_bin_fw_info *)itr = *fw[i];
  1479. +
  1480. + itr += sizeof(struct ipts_bin_fw_info);
  1481. +
  1482. + for (j = 0; j < fw[i]->num_of_data_files; j++) {
  1483. + *(struct ipts_bin_data_file_info *)itr =
  1484. + fw[i]->data_file[j];
  1485. +
  1486. + itr += sizeof(struct ipts_bin_data_file_info);
  1487. + }
  1488. + }
  1489. +
  1490. + return fw_list;
  1491. +}
  1492. +
  1493. +int ipts_request_firmware_config(struct ipts_info *ipts,
  1494. + struct ipts_bin_fw_list **cfg)
  1495. +{
  1496. + int ret;
  1497. + const struct firmware *config_fw = NULL;
  1498. +
  1499. + // Make sure that access to the companion is synchronized
  1500. + mutex_lock(&ipts_companion_lock);
  1501. +
  1502. + // Check if a companion was registered. If not, skip
  1503. + // forward and try to load the firmware config from a file
  1504. + if (ipts_modparams.ignore_companion || ipts_companion == NULL) {
  1505. + mutex_unlock(&ipts_companion_lock);
  1506. + goto config_fallback;
  1507. + }
  1508. +
  1509. + if (ipts_companion->firmware_config != NULL) {
  1510. + *cfg = ipts_alloc_fw_list(ipts_companion->firmware_config);
  1511. + mutex_unlock(&ipts_companion_lock);
  1512. + return 0;
  1513. + }
  1514. +
  1515. +config_fallback:
  1516. +
  1517. + // If fallback loading for the firmware config was disabled, abort.
  1518. + // Return -ENOENT as no config file was found.
  1519. + if (ipts_modparams.ignore_config_fallback)
  1520. + return -ENOENT;
  1521. +
  1522. + // No firmware config was found by the companion driver,
  1523. + // try loading it from a file now
  1524. + ret = ipts_request_firmware(&config_fw, IPTS_FW_CONFIG_FILE,
  1525. + &ipts->cldev->dev);
  1526. + if (!ret)
  1527. + *cfg = (struct ipts_bin_fw_list *)config_fw->data;
  1528. + else
  1529. + release_firmware(config_fw);
  1530. +
  1531. + return ret;
  1532. +
  1533. +}
  1534. diff --git a/drivers/misc/ipts/companion.h b/drivers/misc/ipts/companion.h
  1535. new file mode 100644
  1536. index 0000000000000..7a1e4b388c40a
  1537. --- /dev/null
  1538. +++ b/drivers/misc/ipts/companion.h
  1539. @@ -0,0 +1,25 @@
  1540. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  1541. +/*
  1542. + *
  1543. + * Intel Precise Touch & Stylus
  1544. + * Copyright (c) 2016 Intel Corporation
  1545. + *
  1546. + */
  1547. +
  1548. +#ifndef _IPTS_COMPANION_H_
  1549. +#define _IPTS_COMPANION_H_
  1550. +
  1551. +#include <linux/firmware.h>
  1552. +#include <linux/ipts-binary.h>
  1553. +
  1554. +#include "ipts.h"
  1555. +
  1556. +bool ipts_companion_available(void);
  1557. +
  1558. +int ipts_request_firmware(const struct firmware **fw, const char *name,
  1559. + struct device *device);
  1560. +
  1561. +int ipts_request_firmware_config(struct ipts_info *ipts,
  1562. + struct ipts_bin_fw_list **firmware_config);
  1563. +
  1564. +#endif // _IPTS_COMPANION_H_
  1565. diff --git a/drivers/misc/ipts/companion/Kconfig b/drivers/misc/ipts/companion/Kconfig
  1566. new file mode 100644
  1567. index 0000000000000..ef17d9bb5242f
  1568. --- /dev/null
  1569. +++ b/drivers/misc/ipts/companion/Kconfig
  1570. @@ -0,0 +1,8 @@
  1571. +# SPDX-License-Identifier: GPL-2.0-or-later
  1572. +config INTEL_IPTS_SURFACE
  1573. + tristate "IPTS companion driver for Microsoft Surface"
  1574. + depends on INTEL_IPTS && ACPI
  1575. + help
  1576. + IPTS companion driver for Microsoft Surface. This driver is
  1577. + responsible for loading firmware using surface-specific hardware IDs.
  1578. + If you have a Microsoft Surface using IPTS, select y or m here.
  1579. diff --git a/drivers/misc/ipts/companion/Makefile b/drivers/misc/ipts/companion/Makefile
  1580. new file mode 100644
  1581. index 0000000000000..b37f2f59937a8
  1582. --- /dev/null
  1583. +++ b/drivers/misc/ipts/companion/Makefile
  1584. @@ -0,0 +1,2 @@
  1585. +# SPDX-License-Identifier: GPL-2.0-or-later
  1586. +obj-$(CONFIG_INTEL_IPTS_SURFACE)+= ipts-surface.o
  1587. diff --git a/drivers/misc/ipts/companion/ipts-surface.c b/drivers/misc/ipts/companion/ipts-surface.c
  1588. new file mode 100644
  1589. index 0000000000000..a717dfcdfeba7
  1590. --- /dev/null
  1591. +++ b/drivers/misc/ipts/companion/ipts-surface.c
  1592. @@ -0,0 +1,157 @@
  1593. +// SPDX-License-Identifier: GPL-2.0-or-later
  1594. +/*
  1595. + *
  1596. + * Intel Precise Touch & Stylus
  1597. + * Copyright (c) 2016 Intel Corporation
  1598. + * Copyright (c) 2019 Dorian Stoll
  1599. + *
  1600. + */
  1601. +
  1602. +#include <linux/acpi.h>
  1603. +#include <linux/firmware.h>
  1604. +#include <linux/ipts.h>
  1605. +#include <linux/ipts-companion.h>
  1606. +#include <linux/module.h>
  1607. +#include <linux/platform_device.h>
  1608. +
  1609. +#define IPTS_SURFACE_FW_PATH_FMT "intel/ipts/%s/%s"
  1610. +
  1611. +/*
  1612. + * checkpatch complains about this and wants it wrapped with do { } while(0);
  1613. + * Since this would absolutely not work, just ignore checkpatch in this case.
  1614. + */
  1615. +#define IPTS_SURFACE_FIRMWARE(X) \
  1616. + MODULE_FIRMWARE("intel/ipts/" X "/config.bin"); \
  1617. + MODULE_FIRMWARE("intel/ipts/" X "/intel_desc.bin"); \
  1618. + MODULE_FIRMWARE("intel/ipts/" X "/vendor_desc.bin"); \
  1619. + MODULE_FIRMWARE("intel/ipts/" X "/vendor_kernel.bin")
  1620. +
  1621. +/*
  1622. + * Checkpatch complains about the following lines because it sees them as
  1623. + * header files mixed with .c files. However, forward declaration is perfectly
  1624. + * fine in C, and this allows us to seperate the companion data from the
  1625. + * functions for the companion.
  1626. + */
  1627. +int ipts_surface_request_firmware(struct ipts_companion *companion,
  1628. + const struct firmware **fw, const char *name,
  1629. + struct device *device);
  1630. +
  1631. +unsigned int ipts_surface_get_quirks(struct ipts_companion *companion);
  1632. +
  1633. +static struct ipts_bin_fw_info ipts_surface_vendor_kernel = {
  1634. + .fw_name = "vendor_kernel.bin",
  1635. + .vendor_output = -1,
  1636. + .num_of_data_files = 3,
  1637. + .data_file = {
  1638. + {
  1639. + .io_buffer_type = IPTS_CONFIGURATION,
  1640. + .flags = IPTS_DATA_FILE_FLAG_NONE,
  1641. + .file_name = "config.bin",
  1642. + },
  1643. +
  1644. + // The following files are part of the config, but they don't
  1645. + // exist, and the driver never requests them.
  1646. + {
  1647. + .io_buffer_type = IPTS_CALIBRATION,
  1648. + .flags = IPTS_DATA_FILE_FLAG_NONE,
  1649. + .file_name = "calib.bin",
  1650. + },
  1651. + {
  1652. + .io_buffer_type = IPTS_FEATURE,
  1653. + .flags = IPTS_DATA_FILE_FLAG_SHARE,
  1654. + .file_name = "feature.bin",
  1655. + },
  1656. + },
  1657. +};
  1658. +
  1659. +static struct ipts_bin_fw_info *ipts_surface_fw_config[] = {
  1660. + &ipts_surface_vendor_kernel,
  1661. + NULL,
  1662. +};
  1663. +
  1664. +static struct ipts_companion ipts_surface_companion = {
  1665. + .firmware_request = &ipts_surface_request_firmware,
  1666. + .firmware_config = ipts_surface_fw_config,
  1667. + .name = "ipts_surface",
  1668. +};
  1669. +
  1670. +int ipts_surface_request_firmware(struct ipts_companion *companion,
  1671. + const struct firmware **fw, const char *name,
  1672. + struct device *device)
  1673. +{
  1674. + char fw_path[MAX_IOCL_FILE_PATH_LEN];
  1675. +
  1676. + if (companion == NULL || companion->data == NULL)
  1677. + return -ENOENT;
  1678. +
  1679. + snprintf(fw_path, MAX_IOCL_FILE_PATH_LEN, IPTS_SURFACE_FW_PATH_FMT,
  1680. + (const char *)companion->data, name);
  1681. + return request_firmware(fw, fw_path, device);
  1682. +}
  1683. +
  1684. +static int ipts_surface_probe(struct platform_device *pdev)
  1685. +{
  1686. + int r;
  1687. + struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
  1688. +
  1689. + if (!adev) {
  1690. + dev_err(&pdev->dev, "Unable to find ACPI info for device\n");
  1691. + return -ENODEV;
  1692. + }
  1693. +
  1694. + ipts_surface_companion.data = (void *)acpi_device_hid(adev);
  1695. +
  1696. + r = ipts_add_companion(&ipts_surface_companion);
  1697. + if (r) {
  1698. + dev_warn(&pdev->dev, "Adding IPTS companion failed: %d\n", r);
  1699. + return r;
  1700. + }
  1701. +
  1702. + return 0;
  1703. +}
  1704. +
  1705. +static int ipts_surface_remove(struct platform_device *pdev)
  1706. +{
  1707. + int r = ipts_remove_companion(&ipts_surface_companion);
  1708. +
  1709. + if (r) {
  1710. + dev_warn(&pdev->dev, "Removing IPTS companion failed: %d\n", r);
  1711. + return r;
  1712. + }
  1713. +
  1714. + return 0;
  1715. +}
  1716. +
  1717. +static const struct acpi_device_id ipts_surface_acpi_match[] = {
  1718. + { "MSHW0076", 0 }, // Surface Book 1 / Surface Studio
  1719. + { "MSHW0078", 0 }, // some Surface Pro 4
  1720. + { "MSHW0079", 0 }, // Surface Laptop 1 / 2
  1721. + { "MSHW0101", 0 }, // Surface Book 2 15"
  1722. + { "MSHW0102", 0 }, // Surface Pro 5 / 6
  1723. + { "MSHW0103", 0 }, // some Surface Pro 4
  1724. + { "MSHW0137", 0 }, // Surface Book 2
  1725. + { },
  1726. +};
  1727. +MODULE_DEVICE_TABLE(acpi, ipts_surface_acpi_match);
  1728. +
  1729. +static struct platform_driver ipts_surface_driver = {
  1730. + .probe = ipts_surface_probe,
  1731. + .remove = ipts_surface_remove,
  1732. + .driver = {
  1733. + .name = "ipts_surface",
  1734. + .acpi_match_table = ACPI_PTR(ipts_surface_acpi_match),
  1735. + },
  1736. +};
  1737. +module_platform_driver(ipts_surface_driver);
  1738. +
  1739. +MODULE_AUTHOR("Dorian Stoll <dorian.stoll@tmsp.io>");
  1740. +MODULE_DESCRIPTION("IPTS companion driver for Microsoft Surface");
  1741. +MODULE_LICENSE("GPL v2");
  1742. +
  1743. +IPTS_SURFACE_FIRMWARE("MSHW0076");
  1744. +IPTS_SURFACE_FIRMWARE("MSHW0078");
  1745. +IPTS_SURFACE_FIRMWARE("MSHW0079");
  1746. +IPTS_SURFACE_FIRMWARE("MSHW0101");
  1747. +IPTS_SURFACE_FIRMWARE("MSHW0102");
  1748. +IPTS_SURFACE_FIRMWARE("MSHW0103");
  1749. +IPTS_SURFACE_FIRMWARE("MSHW0137");
  1750. diff --git a/drivers/misc/ipts/dbgfs.c b/drivers/misc/ipts/dbgfs.c
  1751. new file mode 100644
  1752. index 0000000000000..fd9388de17e78
  1753. --- /dev/null
  1754. +++ b/drivers/misc/ipts/dbgfs.c
  1755. @@ -0,0 +1,277 @@
  1756. +// SPDX-License-Identifier: GPL-2.0-or-later
  1757. +/*
  1758. + *
  1759. + * Intel Precise Touch & Stylus
  1760. + * Copyright (c) 2016 Intel Corporation
  1761. + *
  1762. + */
  1763. +
  1764. +#include <linux/ctype.h>
  1765. +#include <linux/debugfs.h>
  1766. +#include <linux/uaccess.h>
  1767. +
  1768. +#include "ipts.h"
  1769. +#include "msg-handler.h"
  1770. +#include "sensor-regs.h"
  1771. +#include "state.h"
  1772. +#include "../mei/mei_dev.h"
  1773. +
  1774. +static const char ipts_status_fmt[] = "ipts state : %01d\n";
  1775. +static const char ipts_debug_fmt[] = ">> tdt : fw status : %s\n"
  1776. + ">> == Doorbell status:%x, count:%x ==\n"
  1777. + ">> == Workqueue head:%u, tail:%u ==\n";
  1778. +
  1779. +static ssize_t ipts_dbgfs_status_read(struct file *fp, char __user *ubuf,
  1780. + size_t cnt, loff_t *ppos)
  1781. +{
  1782. + struct ipts_info *ipts = fp->private_data;
  1783. + char status[256];
  1784. + int len = 0;
  1785. +
  1786. + if (cnt < sizeof(ipts_status_fmt) - 3)
  1787. + return -EINVAL;
  1788. +
  1789. + len = scnprintf(status, 256, ipts_status_fmt, ipts->state);
  1790. + if (len < 0)
  1791. + return -EIO;
  1792. +
  1793. + return simple_read_from_buffer(ubuf, cnt, ppos, status, len);
  1794. +}
  1795. +
  1796. +static const struct file_operations ipts_status_dbgfs_fops = {
  1797. + .open = simple_open,
  1798. + .read = ipts_dbgfs_status_read,
  1799. + .llseek = generic_file_llseek,
  1800. +};
  1801. +
  1802. +static ssize_t ipts_dbgfs_quiesce_io_cmd_write(struct file *fp,
  1803. + const char __user *ubuf, size_t cnt, loff_t *ppos)
  1804. +{
  1805. + struct ipts_info *ipts = fp->private_data;
  1806. + bool result;
  1807. + int rc;
  1808. +
  1809. + rc = kstrtobool_from_user(ubuf, cnt, &result);
  1810. + if (rc)
  1811. + return rc;
  1812. +
  1813. + if (!result)
  1814. + return -EINVAL;
  1815. +
  1816. + ipts_send_sensor_quiesce_io_cmd(ipts);
  1817. + return cnt;
  1818. +}
  1819. +
  1820. +static const struct file_operations ipts_quiesce_io_cmd_dbgfs_fops = {
  1821. + .open = simple_open,
  1822. + .write = ipts_dbgfs_quiesce_io_cmd_write,
  1823. + .llseek = generic_file_llseek,
  1824. +};
  1825. +
  1826. +static ssize_t ipts_dbgfs_clear_mem_window_cmd_write(struct file *fp,
  1827. + const char __user *ubuf, size_t cnt, loff_t *ppos)
  1828. +{
  1829. + struct ipts_info *ipts = fp->private_data;
  1830. + bool result;
  1831. + int rc;
  1832. +
  1833. + rc = kstrtobool_from_user(ubuf, cnt, &result);
  1834. + if (rc)
  1835. + return rc;
  1836. +
  1837. + if (!result)
  1838. + return -EINVAL;
  1839. +
  1840. + ipts_send_sensor_clear_mem_window_cmd(ipts);
  1841. +
  1842. + return cnt;
  1843. +}
  1844. +
  1845. +static const struct file_operations ipts_clear_mem_window_cmd_dbgfs_fops = {
  1846. + .open = simple_open,
  1847. + .write = ipts_dbgfs_clear_mem_window_cmd_write,
  1848. + .llseek = generic_file_llseek,
  1849. +};
  1850. +
  1851. +static ssize_t ipts_dbgfs_debug_read(struct file *fp, char __user *ubuf,
  1852. + size_t cnt, loff_t *ppos)
  1853. +{
  1854. + struct ipts_info *ipts = fp->private_data;
  1855. + char dbg_info[1024];
  1856. + int len = 0;
  1857. +
  1858. + char fw_sts_str[MEI_FW_STATUS_STR_SZ];
  1859. + u32 *db, *head, *tail;
  1860. + struct ipts_wq_info *wq_info;
  1861. +
  1862. + wq_info = &ipts->resource.wq_info;
  1863. + mei_fw_status_str(ipts->cldev->bus, fw_sts_str, MEI_FW_STATUS_STR_SZ);
  1864. +
  1865. + db = (u32 *)wq_info->db_addr;
  1866. + head = (u32 *)wq_info->wq_head_addr;
  1867. + tail = (u32 *)wq_info->wq_tail_addr;
  1868. +
  1869. + if (cnt < sizeof(ipts_debug_fmt) - 3)
  1870. + return -EINVAL;
  1871. +
  1872. + len = scnprintf(dbg_info, 1024, ipts_debug_fmt,
  1873. + fw_sts_str, *db, *(db+1), *head, *tail);
  1874. +
  1875. + if (len < 0)
  1876. + return -EIO;
  1877. +
  1878. + return simple_read_from_buffer(ubuf, cnt, ppos, dbg_info, len);
  1879. +}
  1880. +
  1881. +static const struct file_operations ipts_debug_dbgfs_fops = {
  1882. + .open = simple_open,
  1883. + .read = ipts_dbgfs_debug_read,
  1884. + .llseek = generic_file_llseek,
  1885. +};
  1886. +
  1887. +static ssize_t ipts_dbgfs_ipts_restart_write(struct file *fp,
  1888. + const char __user *ubuf, size_t cnt, loff_t *ppos)
  1889. +{
  1890. + struct ipts_info *ipts = fp->private_data;
  1891. + bool result;
  1892. + int rc;
  1893. +
  1894. + rc = kstrtobool_from_user(ubuf, cnt, &result);
  1895. + if (rc)
  1896. + return rc;
  1897. + if (!result)
  1898. + return -EINVAL;
  1899. +
  1900. + ipts_restart(ipts);
  1901. + return cnt;
  1902. +}
  1903. +
  1904. +static const struct file_operations ipts_ipts_restart_dbgfs_fops = {
  1905. + .open = simple_open,
  1906. + .write = ipts_dbgfs_ipts_restart_write,
  1907. + .llseek = generic_file_llseek,
  1908. +};
  1909. +
  1910. +static ssize_t ipts_dbgfs_ipts_stop_write(struct file *fp,
  1911. + const char __user *ubuf, size_t cnt, loff_t *ppos)
  1912. +{
  1913. + struct ipts_info *ipts = fp->private_data;
  1914. + bool result;
  1915. + int rc;
  1916. +
  1917. + rc = kstrtobool_from_user(ubuf, cnt, &result);
  1918. + if (rc)
  1919. + return rc;
  1920. +
  1921. + if (!result)
  1922. + return -EINVAL;
  1923. +
  1924. + ipts_stop(ipts);
  1925. + return cnt;
  1926. +}
  1927. +
  1928. +static const struct file_operations ipts_ipts_stop_dbgfs_fops = {
  1929. + .open = simple_open,
  1930. + .write = ipts_dbgfs_ipts_stop_write,
  1931. + .llseek = generic_file_llseek,
  1932. +};
  1933. +
  1934. +static ssize_t ipts_dbgfs_ipts_start_write(struct file *fp,
  1935. + const char __user *ubuf, size_t cnt, loff_t *ppos)
  1936. +{
  1937. + struct ipts_info *ipts = fp->private_data;
  1938. + bool result;
  1939. + int rc;
  1940. +
  1941. + rc = kstrtobool_from_user(ubuf, cnt, &result);
  1942. + if (rc)
  1943. + return rc;
  1944. +
  1945. + if (!result)
  1946. + return -EINVAL;
  1947. +
  1948. + ipts_start(ipts);
  1949. + return cnt;
  1950. +}
  1951. +
  1952. +static const struct file_operations ipts_ipts_start_dbgfs_fops = {
  1953. + .open = simple_open,
  1954. + .write = ipts_dbgfs_ipts_start_write,
  1955. + .llseek = generic_file_llseek,
  1956. +};
  1957. +
  1958. +void ipts_dbgfs_deregister(struct ipts_info *ipts)
  1959. +{
  1960. + if (!ipts->dbgfs_dir)
  1961. + return;
  1962. +
  1963. + debugfs_remove_recursive(ipts->dbgfs_dir);
  1964. + ipts->dbgfs_dir = NULL;
  1965. +}
  1966. +
  1967. +int ipts_dbgfs_register(struct ipts_info *ipts, const char *name)
  1968. +{
  1969. + struct dentry *dir, *f;
  1970. +
  1971. + dir = debugfs_create_dir(name, NULL);
  1972. + if (!dir)
  1973. + return -ENOMEM;
  1974. +
  1975. + f = debugfs_create_file("status", 0200, dir, ipts,
  1976. + &ipts_status_dbgfs_fops);
  1977. + if (!f) {
  1978. + ipts_err(ipts, "debugfs status creation failed\n");
  1979. + goto err;
  1980. + }
  1981. +
  1982. + f = debugfs_create_file("quiesce_io_cmd", 0200, dir, ipts,
  1983. + &ipts_quiesce_io_cmd_dbgfs_fops);
  1984. + if (!f) {
  1985. + ipts_err(ipts, "debugfs quiesce_io_cmd creation failed\n");
  1986. + goto err;
  1987. + }
  1988. +
  1989. + f = debugfs_create_file("clear_mem_window_cmd", 0200, dir, ipts,
  1990. + &ipts_clear_mem_window_cmd_dbgfs_fops);
  1991. + if (!f) {
  1992. + ipts_err(ipts, "debugfs clear_mem_window_cmd creation failed\n");
  1993. + goto err;
  1994. + }
  1995. +
  1996. + f = debugfs_create_file("debug", 0200, dir, ipts,
  1997. + &ipts_debug_dbgfs_fops);
  1998. + if (!f) {
  1999. + ipts_err(ipts, "debugfs debug creation failed\n");
  2000. + goto err;
  2001. + }
  2002. +
  2003. + f = debugfs_create_file("ipts_restart", 0200, dir, ipts,
  2004. + &ipts_ipts_restart_dbgfs_fops);
  2005. + if (!f) {
  2006. + ipts_err(ipts, "debugfs ipts_restart creation failed\n");
  2007. + goto err;
  2008. + }
  2009. +
  2010. + f = debugfs_create_file("ipts_stop", 0200, dir, ipts,
  2011. + &ipts_ipts_stop_dbgfs_fops);
  2012. + if (!f) {
  2013. + ipts_err(ipts, "debugfs ipts_stop creation failed\n");
  2014. + goto err;
  2015. + }
  2016. +
  2017. + f = debugfs_create_file("ipts_start", 0200, dir, ipts,
  2018. + &ipts_ipts_start_dbgfs_fops);
  2019. + if (!f) {
  2020. + ipts_err(ipts, "debugfs ipts_start creation failed\n");
  2021. + goto err;
  2022. + }
  2023. +
  2024. + ipts->dbgfs_dir = dir;
  2025. +
  2026. + return 0;
  2027. +
  2028. +err:
  2029. + ipts_dbgfs_deregister(ipts);
  2030. +
  2031. + return -ENODEV;
  2032. +}
  2033. diff --git a/drivers/misc/ipts/gfx.c b/drivers/misc/ipts/gfx.c
  2034. new file mode 100644
  2035. index 0000000000000..b8900f514c756
  2036. --- /dev/null
  2037. +++ b/drivers/misc/ipts/gfx.c
  2038. @@ -0,0 +1,180 @@
  2039. +// SPDX-License-Identifier: GPL-2.0-or-later
  2040. +/*
  2041. + *
  2042. + * Intel Precise Touch & Stylus
  2043. + * Copyright (c) 2016 Intel Corporation
  2044. + *
  2045. + */
  2046. +
  2047. +#include <linux/delay.h>
  2048. +#include <linux/kthread.h>
  2049. +
  2050. +#include "ipts.h"
  2051. +#include "msg-handler.h"
  2052. +#include "params.h"
  2053. +#include "state.h"
  2054. +#include "../mei/mei_dev.h"
  2055. +
  2056. +static void gfx_processing_complete(void *data)
  2057. +{
  2058. + struct ipts_info *ipts = data;
  2059. +
  2060. + if (ipts_get_state(ipts) == IPTS_STA_RAW_DATA_STARTED) {
  2061. + schedule_work(&ipts->raw_data_work);
  2062. + return;
  2063. + }
  2064. +
  2065. + ipts_dbg(ipts, "not ready to handle gfx event\n");
  2066. +}
  2067. +
  2068. +static void notify_gfx_status(u32 status, void *data)
  2069. +{
  2070. + struct ipts_info *ipts = data;
  2071. +
  2072. + ipts->gfx_status = status;
  2073. + schedule_work(&ipts->gfx_status_work);
  2074. +}
  2075. +
  2076. +static int connect_gfx(struct ipts_info *ipts)
  2077. +{
  2078. + int ret = 0;
  2079. + struct ipts_connect connect;
  2080. +
  2081. + connect.client = ipts->cldev->dev.parent;
  2082. + connect.if_version = IPTS_INTERFACE_V1;
  2083. + connect.ipts_cb.workload_complete = gfx_processing_complete;
  2084. + connect.ipts_cb.notify_gfx_status = notify_gfx_status;
  2085. + connect.data = (void *)ipts;
  2086. +
  2087. + ret = ipts_connect(&connect);
  2088. + if (ret)
  2089. + return ret;
  2090. +
  2091. + // TODO: GFX version check
  2092. + ipts->gfx_info.gfx_handle = connect.gfx_handle;
  2093. + ipts->gfx_info.ipts_ops = connect.ipts_ops;
  2094. +
  2095. + return ret;
  2096. +}
  2097. +
  2098. +static void disconnect_gfx(struct ipts_info *ipts)
  2099. +{
  2100. + ipts_disconnect(ipts->gfx_info.gfx_handle);
  2101. +}
  2102. +
  2103. +static struct task_struct *dbg_thread;
  2104. +
  2105. +static void ipts_print_dbg_info(struct ipts_info *ipts)
  2106. +{
  2107. + char fw_sts_str[MEI_FW_STATUS_STR_SZ];
  2108. + u32 *db, *head, *tail;
  2109. + struct ipts_wq_info *wq_info;
  2110. +
  2111. + wq_info = &ipts->resource.wq_info;
  2112. +
  2113. + mei_fw_status_str(ipts->cldev->bus, fw_sts_str, MEI_FW_STATUS_STR_SZ);
  2114. + pr_info(">> tdt : fw status : %s\n", fw_sts_str);
  2115. +
  2116. + db = (u32 *)wq_info->db_addr;
  2117. + head = (u32 *)wq_info->wq_head_addr;
  2118. + tail = (u32 *)wq_info->wq_tail_addr;
  2119. +
  2120. + // Every time the ME has filled up the touch input buffer, and the GuC
  2121. + // doorbell is rang, the doorbell count will increase by one
  2122. + // The workqueue is the queue of touch events that the GuC has to
  2123. + // process. Head is the currently processed event, while tail is
  2124. + // the last one that is currently available. If head and tail are
  2125. + // not equal, this can be an indicator for GuC / GPU hang.
  2126. + pr_info(">> == Doorbell status:%x, count:%x ==\n", *db, *(db+1));
  2127. + pr_info(">> == Workqueue head:%u, tail:%u ==\n", *head, *tail);
  2128. +}
  2129. +
  2130. +static int ipts_dbg_thread(void *data)
  2131. +{
  2132. + struct ipts_info *ipts = (struct ipts_info *)data;
  2133. +
  2134. + pr_info(">> start debug thread\n");
  2135. +
  2136. + while (!kthread_should_stop()) {
  2137. + if (ipts_get_state(ipts) != IPTS_STA_RAW_DATA_STARTED) {
  2138. + pr_info("state is not IPTS_STA_RAW_DATA_STARTED : %d\n",
  2139. + ipts_get_state(ipts));
  2140. +
  2141. + msleep(5000);
  2142. + continue;
  2143. + }
  2144. +
  2145. + ipts_print_dbg_info(ipts);
  2146. + msleep(3000);
  2147. + }
  2148. +
  2149. + return 0;
  2150. +}
  2151. +
  2152. +int ipts_open_gpu(struct ipts_info *ipts)
  2153. +{
  2154. + int ret = 0;
  2155. +
  2156. + ret = connect_gfx(ipts);
  2157. + if (ret) {
  2158. + ipts_dbg(ipts, "cannot connect GPU\n");
  2159. + return ret;
  2160. + }
  2161. +
  2162. + ret = ipts->gfx_info.ipts_ops.get_wq_info(ipts->gfx_info.gfx_handle,
  2163. + &ipts->resource.wq_info);
  2164. + if (ret) {
  2165. + ipts_dbg(ipts, "error in get_wq_info\n");
  2166. + return ret;
  2167. + }
  2168. +
  2169. + if (ipts_modparams.debug_thread)
  2170. + dbg_thread = kthread_run(
  2171. + ipts_dbg_thread, (void *)ipts, "ipts_debug");
  2172. +
  2173. + return 0;
  2174. +}
  2175. +
  2176. +void ipts_close_gpu(struct ipts_info *ipts)
  2177. +{
  2178. + disconnect_gfx(ipts);
  2179. +
  2180. + if (ipts_modparams.debug_thread)
  2181. + kthread_stop(dbg_thread);
  2182. +}
  2183. +
  2184. +struct ipts_mapbuffer *ipts_map_buffer(struct ipts_info *ipts,
  2185. + u32 size, u32 flags)
  2186. +{
  2187. + struct ipts_mapbuffer *buf;
  2188. + u64 handle;
  2189. + int ret;
  2190. +
  2191. + buf = devm_kzalloc(&ipts->cldev->dev, sizeof(*buf), GFP_KERNEL);
  2192. + if (!buf)
  2193. + return NULL;
  2194. +
  2195. + buf->size = size;
  2196. + buf->flags = flags;
  2197. +
  2198. + handle = ipts->gfx_info.gfx_handle;
  2199. + ret = ipts->gfx_info.ipts_ops.map_buffer(handle, buf);
  2200. + if (ret) {
  2201. + devm_kfree(&ipts->cldev->dev, buf);
  2202. + return NULL;
  2203. + }
  2204. +
  2205. + return buf;
  2206. +}
  2207. +
  2208. +void ipts_unmap_buffer(struct ipts_info *ipts, struct ipts_mapbuffer *buf)
  2209. +{
  2210. + u64 handle;
  2211. +
  2212. + if (!buf)
  2213. + return;
  2214. +
  2215. + handle = ipts->gfx_info.gfx_handle;
  2216. + ipts->gfx_info.ipts_ops.unmap_buffer(handle, buf->buf_handle);
  2217. + devm_kfree(&ipts->cldev->dev, buf);
  2218. +}
  2219. diff --git a/drivers/misc/ipts/gfx.h b/drivers/misc/ipts/gfx.h
  2220. new file mode 100644
  2221. index 0000000000000..2880e122e9f96
  2222. --- /dev/null
  2223. +++ b/drivers/misc/ipts/gfx.h
  2224. @@ -0,0 +1,25 @@
  2225. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  2226. +/*
  2227. + *
  2228. + * Intel Precise Touch & Stylus
  2229. + * Copyright (c) 2016 Intel Corporation
  2230. + *
  2231. + */
  2232. +
  2233. +#ifndef _IPTS_GFX_H_
  2234. +#define _IPTS_GFX_H_
  2235. +
  2236. +#include <linux/ipts-gfx.h>
  2237. +
  2238. +#include "ipts.h"
  2239. +
  2240. +int ipts_open_gpu(struct ipts_info *ipts);
  2241. +void ipts_close_gpu(struct ipts_info *ipts);
  2242. +
  2243. +struct ipts_mapbuffer *ipts_map_buffer(struct ipts_info *ipts,
  2244. + u32 size, u32 flags);
  2245. +
  2246. +void ipts_unmap_buffer(struct ipts_info *ipts,
  2247. + struct ipts_mapbuffer *buf);
  2248. +
  2249. +#endif // _IPTS_GFX_H_
  2250. diff --git a/drivers/misc/ipts/hid.c b/drivers/misc/ipts/hid.c
  2251. new file mode 100644
  2252. index 0000000000000..1b7ad2a774a86
  2253. --- /dev/null
  2254. +++ b/drivers/misc/ipts/hid.c
  2255. @@ -0,0 +1,469 @@
  2256. +// SPDX-License-Identifier: GPL-2.0-or-later
  2257. +/*
  2258. + *
  2259. + * Intel Precise Touch & Stylus
  2260. + * Copyright (c) 2016 Intel Corporation
  2261. + *
  2262. + */
  2263. +
  2264. +#include <linux/dmi.h>
  2265. +#include <linux/firmware.h>
  2266. +#include <linux/hid.h>
  2267. +#include <linux/ipts.h>
  2268. +#include <linux/module.h>
  2269. +#include <linux/vmalloc.h>
  2270. +
  2271. +#include "companion.h"
  2272. +#include "hid.h"
  2273. +#include "ipts.h"
  2274. +#include "msg-handler.h"
  2275. +#include "params.h"
  2276. +#include "resource.h"
  2277. +#include "sensor-regs.h"
  2278. +
  2279. +#define HID_DESC_INTEL "intel_desc.bin"
  2280. +#define HID_DESC_VENDOR "vendor_desc.bin"
  2281. +
  2282. +enum output_buffer_payload_type {
  2283. + OUTPUT_BUFFER_PAYLOAD_ERROR = 0,
  2284. + OUTPUT_BUFFER_PAYLOAD_HID_INPUT_REPORT,
  2285. + OUTPUT_BUFFER_PAYLOAD_HID_FEATURE_REPORT,
  2286. + OUTPUT_BUFFER_PAYLOAD_KERNEL_LOAD,
  2287. + OUTPUT_BUFFER_PAYLOAD_FEEDBACK_BUFFER
  2288. +};
  2289. +
  2290. +struct kernel_output_buffer_header {
  2291. + u16 length;
  2292. + u8 payload_type;
  2293. + u8 reserved1;
  2294. + struct touch_hid_private_data hid_private_data;
  2295. + u8 reserved2[28];
  2296. + u8 data[0];
  2297. +};
  2298. +
  2299. +struct kernel_output_payload_error {
  2300. + u16 severity;
  2301. + u16 source;
  2302. + u8 code[4];
  2303. + char string[128];
  2304. +};
  2305. +
  2306. +static int ipts_hid_get_descriptor(struct ipts_info *ipts,
  2307. + u8 **desc, int *size)
  2308. +{
  2309. + u8 *buf;
  2310. + int hid_size = 0, ret = 0;
  2311. + const struct firmware *intel_desc = NULL;
  2312. + const struct firmware *vendor_desc = NULL;
  2313. +
  2314. + ret = ipts_request_firmware(&intel_desc, HID_DESC_INTEL,
  2315. + &ipts->cldev->dev);
  2316. + if (ret)
  2317. + goto no_hid;
  2318. +
  2319. + hid_size = intel_desc->size;
  2320. +
  2321. + ret = ipts_request_firmware(&vendor_desc, HID_DESC_VENDOR,
  2322. + &ipts->cldev->dev);
  2323. + if (ret)
  2324. + ipts_dbg(ipts, "error in reading HID Vendor Descriptor\n");
  2325. + else
  2326. + hid_size += vendor_desc->size;
  2327. +
  2328. + ipts_dbg(ipts, "HID descriptor size = %d\n", hid_size);
  2329. +
  2330. + buf = vmalloc(hid_size);
  2331. + if (buf == NULL) {
  2332. + ret = -ENOMEM;
  2333. + goto no_mem;
  2334. + }
  2335. +
  2336. + memcpy(buf, intel_desc->data, intel_desc->size);
  2337. + if (vendor_desc) {
  2338. + memcpy(&buf[intel_desc->size], vendor_desc->data,
  2339. + vendor_desc->size);
  2340. + release_firmware(vendor_desc);
  2341. + }
  2342. + release_firmware(intel_desc);
  2343. +
  2344. + *desc = buf;
  2345. + *size = hid_size;
  2346. +
  2347. + return 0;
  2348. +
  2349. +no_mem:
  2350. + if (vendor_desc)
  2351. + release_firmware(vendor_desc);
  2352. +
  2353. + release_firmware(intel_desc);
  2354. +
  2355. +no_hid:
  2356. + return ret;
  2357. +}
  2358. +
  2359. +static int ipts_hid_parse(struct hid_device *hid)
  2360. +{
  2361. + struct ipts_info *ipts = hid->driver_data;
  2362. + int ret = 0, size;
  2363. + u8 *buf;
  2364. +
  2365. + ipts_dbg(ipts, "%s() start\n", __func__);
  2366. +
  2367. + ret = ipts_hid_get_descriptor(ipts, &buf, &size);
  2368. + if (ret != 0) {
  2369. + ipts_dbg(ipts, "ipts_hid_get_descriptor: %d\n",
  2370. + ret);
  2371. + return -EIO;
  2372. + }
  2373. +
  2374. + ret = hid_parse_report(hid, buf, size);
  2375. + vfree(buf);
  2376. + if (ret) {
  2377. + ipts_err(ipts, "hid_parse_report error : %d\n", ret);
  2378. + return ret;
  2379. + }
  2380. +
  2381. + ipts->hid_desc_ready = true;
  2382. +
  2383. + return 0;
  2384. +}
  2385. +
  2386. +static int ipts_hid_start(struct hid_device *hid)
  2387. +{
  2388. + return 0;
  2389. +}
  2390. +
  2391. +static void ipts_hid_stop(struct hid_device *hid)
  2392. +{
  2393. +
  2394. +}
  2395. +
  2396. +static int ipts_hid_open(struct hid_device *hid)
  2397. +{
  2398. + return 0;
  2399. +}
  2400. +
  2401. +static void ipts_hid_close(struct hid_device *hid)
  2402. +{
  2403. + struct ipts_info *ipts = hid->driver_data;
  2404. +
  2405. + ipts->hid_desc_ready = false;
  2406. +}
  2407. +
  2408. +static int ipts_hid_send_hid2me_feedback(struct ipts_info *ipts,
  2409. + u32 fb_data_type, __u8 *buf, size_t count)
  2410. +{
  2411. + struct ipts_buffer_info *fb_buf;
  2412. + struct touch_feedback_hdr *feedback;
  2413. + enum ipts_state state;
  2414. + u8 *payload;
  2415. + int header_size;
  2416. +
  2417. + header_size = sizeof(struct touch_feedback_hdr);
  2418. +
  2419. + if (count > ipts->resource.hid2me_buffer_size - header_size)
  2420. + return -EINVAL;
  2421. +
  2422. + state = ipts_get_state(ipts);
  2423. + if (state != IPTS_STA_RAW_DATA_STARTED &&
  2424. + state != IPTS_STA_HID_STARTED)
  2425. + return 0;
  2426. +
  2427. + fb_buf = ipts_get_hid2me_buffer(ipts);
  2428. + feedback = (struct touch_feedback_hdr *)fb_buf->addr;
  2429. + payload = fb_buf->addr + header_size;
  2430. + memset(feedback, 0, header_size);
  2431. +
  2432. + feedback->feedback_data_type = fb_data_type;
  2433. + feedback->feedback_cmd_type = TOUCH_FEEDBACK_CMD_TYPE_NONE;
  2434. + feedback->payload_size_bytes = count;
  2435. + feedback->buffer_id = TOUCH_HID_2_ME_BUFFER_ID;
  2436. + feedback->protocol_ver = 0;
  2437. + feedback->reserved[0] = 0xAC;
  2438. +
  2439. + // copy payload
  2440. + memcpy(payload, buf, count);
  2441. +
  2442. + ipts_send_feedback(ipts, TOUCH_HID_2_ME_BUFFER_ID, 0);
  2443. +
  2444. + return 0;
  2445. +}
  2446. +
  2447. +static int ipts_hid_raw_request(struct hid_device *hid,
  2448. + unsigned char report_number, __u8 *buf, size_t count,
  2449. + unsigned char report_type, int reqtype)
  2450. +{
  2451. + struct ipts_info *ipts = hid->driver_data;
  2452. + u32 fb_data_type;
  2453. +
  2454. + ipts_dbg(ipts, "hid raw request => report %d, request %d\n",
  2455. + (int)report_type, reqtype);
  2456. +
  2457. + if (report_type != HID_FEATURE_REPORT)
  2458. + return 0;
  2459. +
  2460. + switch (reqtype) {
  2461. + case HID_REQ_GET_REPORT:
  2462. + fb_data_type = TOUCH_FEEDBACK_DATA_TYPE_GET_FEATURES;
  2463. + break;
  2464. + case HID_REQ_SET_REPORT:
  2465. + fb_data_type = TOUCH_FEEDBACK_DATA_TYPE_SET_FEATURES;
  2466. + break;
  2467. + default:
  2468. + ipts_err(ipts, "raw request not supprted: %d\n", reqtype);
  2469. + return -EIO;
  2470. + }
  2471. +
  2472. + return ipts_hid_send_hid2me_feedback(ipts, fb_data_type, buf, count);
  2473. +}
  2474. +
  2475. +static int ipts_hid_output_report(struct hid_device *hid,
  2476. + __u8 *buf, size_t count)
  2477. +{
  2478. + struct ipts_info *ipts = hid->driver_data;
  2479. + u32 fb_data_type;
  2480. +
  2481. + ipts_dbg(ipts, "hid output report\n");
  2482. +
  2483. + fb_data_type = TOUCH_FEEDBACK_DATA_TYPE_OUTPUT_REPORT;
  2484. +
  2485. + return ipts_hid_send_hid2me_feedback(ipts, fb_data_type, buf, count);
  2486. +}
  2487. +
  2488. +static struct hid_ll_driver ipts_hid_ll_driver = {
  2489. + .parse = ipts_hid_parse,
  2490. + .start = ipts_hid_start,
  2491. + .stop = ipts_hid_stop,
  2492. + .open = ipts_hid_open,
  2493. + .close = ipts_hid_close,
  2494. + .raw_request = ipts_hid_raw_request,
  2495. + .output_report = ipts_hid_output_report,
  2496. +};
  2497. +
  2498. +int ipts_hid_init(struct ipts_info *ipts)
  2499. +{
  2500. + int ret = 0;
  2501. + struct hid_device *hid;
  2502. +
  2503. + hid = hid_allocate_device();
  2504. + if (IS_ERR(hid))
  2505. + return PTR_ERR(hid);
  2506. +
  2507. + hid->driver_data = ipts;
  2508. + hid->ll_driver = &ipts_hid_ll_driver;
  2509. + hid->dev.parent = &ipts->cldev->dev;
  2510. + hid->bus = BUS_MEI;
  2511. + hid->version = ipts->device_info.fw_rev;
  2512. + hid->vendor = ipts->device_info.vendor_id;
  2513. + hid->product = ipts->device_info.device_id;
  2514. +
  2515. + snprintf(hid->phys, sizeof(hid->phys), "heci3");
  2516. + snprintf(hid->name, sizeof(hid->name),
  2517. + "ipts %04hX:%04hX", hid->vendor, hid->product);
  2518. +
  2519. + ret = hid_add_device(hid);
  2520. + if (ret) {
  2521. + if (ret != -ENODEV)
  2522. + ipts_err(ipts, "can't add hid device: %d\n", ret);
  2523. +
  2524. + hid_destroy_device(hid);
  2525. +
  2526. + return ret;
  2527. + }
  2528. +
  2529. + ipts->hid = hid;
  2530. +
  2531. + return 0;
  2532. +}
  2533. +
  2534. +void ipts_hid_release(struct ipts_info *ipts)
  2535. +{
  2536. + if (!ipts->hid)
  2537. + return;
  2538. +
  2539. + hid_destroy_device(ipts->hid);
  2540. +}
  2541. +
  2542. +int ipts_handle_hid_data(struct ipts_info *ipts,
  2543. + struct touch_sensor_hid_ready_for_data_rsp_data *hid_rsp)
  2544. +{
  2545. + struct touch_raw_data_hdr *raw_header;
  2546. + struct ipts_buffer_info *buffer_info;
  2547. + struct touch_feedback_hdr *feedback;
  2548. + u8 *raw_data;
  2549. + int touch_data_buffer_index;
  2550. + int transaction_id;
  2551. + int ret = 0;
  2552. +
  2553. + touch_data_buffer_index = (int)hid_rsp->touch_data_buffer_index;
  2554. + buffer_info = ipts_get_touch_data_buffer_hid(ipts);
  2555. + raw_header = (struct touch_raw_data_hdr *)buffer_info->addr;
  2556. + transaction_id = raw_header->hid_private_data.transaction_id;
  2557. + raw_data = (u8 *)raw_header + sizeof(struct touch_raw_data_hdr);
  2558. +
  2559. + switch (raw_header->data_type) {
  2560. + case TOUCH_RAW_DATA_TYPE_HID_REPORT: {
  2561. + if (raw_header->raw_data_size_bytes > HID_MAX_BUFFER_SIZE) {
  2562. + ipts_err(ipts, "input report too large (%u bytes), skipping",
  2563. + raw_header->raw_data_size_bytes);
  2564. + break;
  2565. + }
  2566. +
  2567. + memcpy(ipts->hid_input_report, raw_data,
  2568. + raw_header->raw_data_size_bytes);
  2569. +
  2570. + ret = hid_input_report(ipts->hid, HID_INPUT_REPORT,
  2571. + (u8 *)ipts->hid_input_report,
  2572. + raw_header->raw_data_size_bytes, 1);
  2573. + if (ret)
  2574. + ipts_err(ipts, "error in hid_input_report: %d\n", ret);
  2575. +
  2576. + break;
  2577. + }
  2578. + case TOUCH_RAW_DATA_TYPE_GET_FEATURES: {
  2579. + // TODO: implement together with "get feature ioctl"
  2580. + break;
  2581. + }
  2582. + case TOUCH_RAW_DATA_TYPE_ERROR: {
  2583. + struct touch_error *touch_err = (struct touch_error *)raw_data;
  2584. +
  2585. + ipts_err(ipts, "error type: %d, me error: %x, err reg: %x\n",
  2586. + touch_err->touch_error_type,
  2587. + touch_err->touch_me_fw_error.value,
  2588. + touch_err->touch_error_register.reg_value);
  2589. +
  2590. + break;
  2591. + }
  2592. + default:
  2593. + break;
  2594. + }
  2595. +
  2596. + // send feedback data for HID mode
  2597. + buffer_info = ipts_get_feedback_buffer(ipts, touch_data_buffer_index);
  2598. + feedback = (struct touch_feedback_hdr *)buffer_info->addr;
  2599. + memset(feedback, 0, sizeof(struct touch_feedback_hdr));
  2600. + feedback->feedback_cmd_type = TOUCH_FEEDBACK_CMD_TYPE_NONE;
  2601. + feedback->payload_size_bytes = 0;
  2602. + feedback->buffer_id = touch_data_buffer_index;
  2603. + feedback->protocol_ver = 0;
  2604. + feedback->reserved[0] = 0xAC;
  2605. +
  2606. + ret = ipts_send_feedback(ipts, touch_data_buffer_index, transaction_id);
  2607. +
  2608. + return ret;
  2609. +}
  2610. +
  2611. +static int handle_outputs(struct ipts_info *ipts, int parallel_idx)
  2612. +{
  2613. + struct kernel_output_buffer_header *out_buf_hdr;
  2614. + struct ipts_buffer_info *output_buf;
  2615. + u8 *input_report, *payload;
  2616. + u8 tr_id;
  2617. + int i, payload_size, header_size;
  2618. + bool send_feedback = false;
  2619. +
  2620. + header_size = sizeof(struct kernel_output_buffer_header);
  2621. + output_buf = ipts_get_output_buffers_by_parallel_id(ipts,
  2622. + parallel_idx);
  2623. +
  2624. + for (i = 0; i < ipts->resource.num_of_outputs; i++) {
  2625. + out_buf_hdr = (struct kernel_output_buffer_header *)
  2626. + output_buf[i].addr;
  2627. +
  2628. + if (out_buf_hdr->length < header_size)
  2629. + continue;
  2630. +
  2631. + tr_id = *(u8 *)&out_buf_hdr->hid_private_data.transaction_id;
  2632. + send_feedback = true;
  2633. +
  2634. + payload_size = out_buf_hdr->length - header_size;
  2635. + payload = out_buf_hdr->data;
  2636. +
  2637. + switch (out_buf_hdr->payload_type) {
  2638. + case OUTPUT_BUFFER_PAYLOAD_HID_INPUT_REPORT: {
  2639. + input_report = ipts->hid_input_report;
  2640. + memcpy(input_report, payload, payload_size);
  2641. +
  2642. + hid_input_report(ipts->hid, HID_INPUT_REPORT,
  2643. + input_report, payload_size, 1);
  2644. +
  2645. + break;
  2646. + }
  2647. + case OUTPUT_BUFFER_PAYLOAD_HID_FEATURE_REPORT: {
  2648. + ipts_dbg(ipts, "output hid feature report\n");
  2649. + break;
  2650. + }
  2651. + case OUTPUT_BUFFER_PAYLOAD_KERNEL_LOAD: {
  2652. + ipts_dbg(ipts, "output kernel load\n");
  2653. + break;
  2654. + }
  2655. + case OUTPUT_BUFFER_PAYLOAD_FEEDBACK_BUFFER: {
  2656. + // Ignored
  2657. + break;
  2658. + }
  2659. + case OUTPUT_BUFFER_PAYLOAD_ERROR: {
  2660. + struct kernel_output_payload_error *err_payload;
  2661. +
  2662. + if (payload_size == 0)
  2663. + break;
  2664. +
  2665. + err_payload = (struct kernel_output_payload_error *)
  2666. + payload;
  2667. +
  2668. + ipts_err(ipts, "severity: %d, source: %d ",
  2669. + err_payload->severity,
  2670. + err_payload->source);
  2671. + ipts_err(ipts, "code : %d:%d:%d:%d\nstring %s\n",
  2672. + err_payload->code[0],
  2673. + err_payload->code[1],
  2674. + err_payload->code[2],
  2675. + err_payload->code[3],
  2676. + err_payload->string);
  2677. +
  2678. + break;
  2679. + }
  2680. + default:
  2681. + ipts_err(ipts, "invalid output buffer payload\n");
  2682. + break;
  2683. + }
  2684. + }
  2685. +
  2686. +
  2687. +
  2688. + if (send_feedback)
  2689. + return ipts_send_feedback(ipts, parallel_idx, tr_id);
  2690. +
  2691. + return 0;
  2692. +}
  2693. +
  2694. +static int handle_output_buffers(struct ipts_info *ipts,
  2695. + int cur_idx, int end_idx)
  2696. +{
  2697. + int max_num_of_buffers = ipts_get_num_of_parallel_buffers(ipts);
  2698. +
  2699. + do {
  2700. + cur_idx++; // cur_idx has last completed so starts with +1
  2701. + cur_idx %= max_num_of_buffers;
  2702. + handle_outputs(ipts, cur_idx);
  2703. + } while (cur_idx != end_idx);
  2704. +
  2705. + return 0;
  2706. +}
  2707. +
  2708. +int ipts_handle_processed_data(struct ipts_info *ipts)
  2709. +{
  2710. + int ret = 0;
  2711. + int current_buffer_idx;
  2712. + int last_buffer_idx;
  2713. +
  2714. + current_buffer_idx = *ipts->last_submitted_id;
  2715. + last_buffer_idx = ipts->last_buffer_completed;
  2716. +
  2717. + if (current_buffer_idx == last_buffer_idx)
  2718. + return 0;
  2719. +
  2720. + ipts->last_buffer_completed = current_buffer_idx;
  2721. + handle_output_buffers(ipts, last_buffer_idx, current_buffer_idx);
  2722. +
  2723. + return ret;
  2724. +}
  2725. diff --git a/drivers/misc/ipts/hid.h b/drivers/misc/ipts/hid.h
  2726. new file mode 100644
  2727. index 0000000000000..c943979e01983
  2728. --- /dev/null
  2729. +++ b/drivers/misc/ipts/hid.h
  2730. @@ -0,0 +1,21 @@
  2731. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  2732. +/*
  2733. + *
  2734. + * Intel Precise Touch & Stylus
  2735. + * Copyright (c) 2016 Intel Corporation
  2736. + *
  2737. + */
  2738. +
  2739. +#ifndef _IPTS_HID_H_
  2740. +#define _IPTS_HID_H_
  2741. +
  2742. +#include "ipts.h"
  2743. +
  2744. +#define BUS_MEI 0x44
  2745. +
  2746. +int ipts_hid_init(struct ipts_info *ipts);
  2747. +void ipts_hid_release(struct ipts_info *ipts);
  2748. +int ipts_handle_hid_data(struct ipts_info *ipts,
  2749. + struct touch_sensor_hid_ready_for_data_rsp_data *hid_rsp);
  2750. +
  2751. +#endif // _IPTS_HID_H_
  2752. diff --git a/drivers/misc/ipts/ipts.c b/drivers/misc/ipts/ipts.c
  2753. new file mode 100644
  2754. index 0000000000000..dfafabf8dd949
  2755. --- /dev/null
  2756. +++ b/drivers/misc/ipts/ipts.c
  2757. @@ -0,0 +1,62 @@
  2758. +// SPDX-License-Identifier: GPL-2.0-or-later
  2759. +/*
  2760. + *
  2761. + * Intel Precise Touch & Stylus
  2762. + * Copyright (c) 2016 Intel Corporation
  2763. + *
  2764. + */
  2765. +
  2766. +#include <linux/device.h>
  2767. +#include <stdarg.h>
  2768. +
  2769. +#include "ipts.h"
  2770. +#include "params.h"
  2771. +
  2772. +static void ipts_printk(const char *level, const struct device *dev,
  2773. + struct va_format *vaf)
  2774. +{
  2775. + if (dev) {
  2776. + dev_printk_emit(level[1] - '0', dev, "%s %s: %pV",
  2777. + dev_driver_string(dev), dev_name(dev), vaf);
  2778. + } else {
  2779. + // checkpatch wants this to be prefixed with KERN_*, but
  2780. + // since the level is passed as a parameter, ignore it
  2781. + printk("%s(NULL device *): %pV", level, vaf);
  2782. + }
  2783. +}
  2784. +
  2785. +void ipts_info(struct ipts_info *ipts, const char *fmt, ...)
  2786. +{
  2787. + va_list args;
  2788. + struct va_format vaf;
  2789. +
  2790. + if (!ipts_modparams.debug)
  2791. + return;
  2792. +
  2793. + va_start(args, fmt);
  2794. +
  2795. + vaf.fmt = fmt;
  2796. + vaf.va = &args;
  2797. +
  2798. + ipts_printk(KERN_INFO, &ipts->cldev->dev, &vaf);
  2799. +
  2800. + va_end(args);
  2801. +}
  2802. +
  2803. +void ipts_dbg(struct ipts_info *ipts, const char *fmt, ...)
  2804. +{
  2805. + va_list args;
  2806. + struct va_format vaf;
  2807. +
  2808. + if (!ipts_modparams.debug)
  2809. + return;
  2810. +
  2811. + va_start(args, fmt);
  2812. +
  2813. + vaf.fmt = fmt;
  2814. + vaf.va = &args;
  2815. +
  2816. + ipts_printk(KERN_DEBUG, &ipts->cldev->dev, &vaf);
  2817. +
  2818. + va_end(args);
  2819. +}
  2820. diff --git a/drivers/misc/ipts/ipts.h b/drivers/misc/ipts/ipts.h
  2821. new file mode 100644
  2822. index 0000000000000..32eb3ffd68a3b
  2823. --- /dev/null
  2824. +++ b/drivers/misc/ipts/ipts.h
  2825. @@ -0,0 +1,172 @@
  2826. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  2827. +/*
  2828. + *
  2829. + * Intel Precise Touch & Stylus
  2830. + * Copyright (c) 2016 Intel Corporation
  2831. + *
  2832. + */
  2833. +
  2834. +#ifndef _IPTS_H_
  2835. +#define _IPTS_H_
  2836. +
  2837. +#include <linux/hid.h>
  2838. +#include <linux/ipts-binary.h>
  2839. +#include <linux/ipts-gfx.h>
  2840. +#include <linux/mei_cl_bus.h>
  2841. +#include <linux/types.h>
  2842. +
  2843. +#include "mei-msgs.h"
  2844. +#include "state.h"
  2845. +
  2846. +#define HID_PARALLEL_DATA_BUFFERS TOUCH_SENSOR_MAX_DATA_BUFFERS
  2847. +
  2848. +#define IPTS_MAX_RETRY 3
  2849. +
  2850. +struct ipts_buffer_info {
  2851. + char *addr;
  2852. + dma_addr_t dma_addr;
  2853. +};
  2854. +
  2855. +struct ipts_gfx_info {
  2856. + u64 gfx_handle;
  2857. + struct ipts_ops ipts_ops;
  2858. +};
  2859. +
  2860. +struct ipts_resource {
  2861. + // ME & GFX resource
  2862. + struct ipts_buffer_info touch_data_buffer_raw
  2863. + [HID_PARALLEL_DATA_BUFFERS];
  2864. + struct ipts_buffer_info touch_data_buffer_hid;
  2865. + struct ipts_buffer_info feedback_buffer[HID_PARALLEL_DATA_BUFFERS];
  2866. + struct ipts_buffer_info hid2me_buffer;
  2867. + u32 hid2me_buffer_size;
  2868. +
  2869. + u8 wq_item_size;
  2870. + struct ipts_wq_info wq_info;
  2871. +
  2872. + // ME2HID buffer
  2873. + char *me2hid_buffer;
  2874. +
  2875. + // GFX specific resource
  2876. + struct ipts_buffer_info raw_data_mode_output_buffer
  2877. + [HID_PARALLEL_DATA_BUFFERS][MAX_NUM_OUTPUT_BUFFERS];
  2878. +
  2879. + int num_of_outputs;
  2880. + bool default_resource_ready;
  2881. + bool raw_data_resource_ready;
  2882. +};
  2883. +
  2884. +struct ipts_info {
  2885. + struct mei_cl_device *cldev;
  2886. + struct hid_device *hid;
  2887. +
  2888. + struct work_struct init_work;
  2889. + struct work_struct raw_data_work;
  2890. + struct work_struct gfx_status_work;
  2891. +
  2892. + struct task_struct *event_loop;
  2893. +
  2894. +#if IS_ENABLED(CONFIG_DEBUG_FS)
  2895. + struct dentry *dbgfs_dir;
  2896. +#endif
  2897. +
  2898. + enum ipts_state state;
  2899. +
  2900. + enum touch_sensor_mode sensor_mode;
  2901. + struct touch_sensor_get_device_info_rsp_data device_info;
  2902. + struct ipts_resource resource;
  2903. + u8 hid_input_report[HID_MAX_BUFFER_SIZE];
  2904. + int num_of_parallel_data_buffers;
  2905. + bool hid_desc_ready;
  2906. +
  2907. + int current_buffer_index;
  2908. + int last_buffer_completed;
  2909. + int *last_submitted_id;
  2910. +
  2911. + struct ipts_gfx_info gfx_info;
  2912. + u64 kernel_handle;
  2913. + int gfx_status;
  2914. + bool display_status;
  2915. +
  2916. + bool restart;
  2917. +};
  2918. +
  2919. +#if IS_ENABLED(CONFIG_DEBUG_FS)
  2920. +int ipts_dbgfs_register(struct ipts_info *ipts, const char *name);
  2921. +void ipts_dbgfs_deregister(struct ipts_info *ipts);
  2922. +#else
  2923. +static int ipts_dbgfs_register(struct ipts_info *ipts, const char *name);
  2924. +static void ipts_dbgfs_deregister(struct ipts_info *ipts);
  2925. +#endif
  2926. +
  2927. +void ipts_info(struct ipts_info *ipts, const char *fmt, ...);
  2928. +void ipts_dbg(struct ipts_info *ipts, const char *fmt, ...);
  2929. +
  2930. +// Because ipts_err is unconditional, this can stay a macro for now
  2931. +#define ipts_err(ipts, format, arg...) \
  2932. + dev_err(&ipts->cldev->dev, format, ##arg)
  2933. +
  2934. +/*
  2935. + * Inline functions
  2936. + */
  2937. +static inline void ipts_set_state(struct ipts_info *ipts,
  2938. + enum ipts_state state)
  2939. +{
  2940. + ipts->state = state;
  2941. +}
  2942. +
  2943. +static inline enum ipts_state ipts_get_state(const struct ipts_info *ipts)
  2944. +{
  2945. + return ipts->state;
  2946. +}
  2947. +
  2948. +static inline bool ipts_is_default_resource_ready(const struct ipts_info *ipts)
  2949. +{
  2950. + return ipts->resource.default_resource_ready;
  2951. +}
  2952. +
  2953. +static inline bool ipts_is_raw_data_resource_ready(const struct ipts_info *ipts)
  2954. +{
  2955. + return ipts->resource.raw_data_resource_ready;
  2956. +}
  2957. +
  2958. +static inline struct ipts_buffer_info *ipts_get_feedback_buffer(
  2959. + struct ipts_info *ipts, int buffer_idx)
  2960. +{
  2961. + return &ipts->resource.feedback_buffer[buffer_idx];
  2962. +}
  2963. +
  2964. +static inline struct ipts_buffer_info *ipts_get_touch_data_buffer_hid(
  2965. + struct ipts_info *ipts)
  2966. +{
  2967. + return &ipts->resource.touch_data_buffer_hid;
  2968. +}
  2969. +
  2970. +static inline struct ipts_buffer_info *ipts_get_output_buffers_by_parallel_id(
  2971. + struct ipts_info *ipts, int parallel_idx)
  2972. +{
  2973. + return &ipts->resource.raw_data_mode_output_buffer[parallel_idx][0];
  2974. +}
  2975. +
  2976. +static inline struct ipts_buffer_info *ipts_get_hid2me_buffer(
  2977. + struct ipts_info *ipts)
  2978. +{
  2979. + return &ipts->resource.hid2me_buffer;
  2980. +}
  2981. +
  2982. +static inline void ipts_set_wq_item_size(struct ipts_info *ipts, u8 size)
  2983. +{
  2984. + ipts->resource.wq_item_size = size;
  2985. +}
  2986. +
  2987. +static inline u8 ipts_get_wq_item_size(const struct ipts_info *ipts)
  2988. +{
  2989. + return ipts->resource.wq_item_size;
  2990. +}
  2991. +
  2992. +static inline int ipts_get_num_of_parallel_buffers(const struct ipts_info *ipts)
  2993. +{
  2994. + return ipts->num_of_parallel_data_buffers;
  2995. +}
  2996. +
  2997. +#endif // _IPTS_H_
  2998. diff --git a/drivers/misc/ipts/kernel.c b/drivers/misc/ipts/kernel.c
  2999. new file mode 100644
  3000. index 0000000000000..a2c43228e2c7d
  3001. --- /dev/null
  3002. +++ b/drivers/misc/ipts/kernel.c
  3003. @@ -0,0 +1,1047 @@
  3004. +// SPDX-License-Identifier: GPL-2.0-or-later
  3005. +/*
  3006. + *
  3007. + * Intel Precise Touch & Stylus
  3008. + * Copyright (c) 2016 Intel Corporation
  3009. + *
  3010. + */
  3011. +
  3012. +#include <linux/module.h>
  3013. +#include <linux/firmware.h>
  3014. +#include <linux/ipts.h>
  3015. +#include <linux/ipts-binary.h>
  3016. +#include <linux/vmalloc.h>
  3017. +
  3018. +#include "companion.h"
  3019. +#include "gfx.h"
  3020. +#include "ipts.h"
  3021. +#include "msg-handler.h"
  3022. +#include "resource.h"
  3023. +#include "state.h"
  3024. +
  3025. +#define BDW_SURFACE_BASE_ADDRESS 0x6101000e
  3026. +#define SURFACE_STATE_OFFSET_WORD 4
  3027. +#define SBA_OFFSET_BYTES 16384
  3028. +#define LASTSUBMITID_DEFAULT_VALUE -1
  3029. +
  3030. +#define IPTS_INPUT_ON ((u32)1 << IPTS_INPUT)
  3031. +#define IPTS_OUTPUT_ON ((u32)1 << IPTS_OUTPUT)
  3032. +#define IPTS_CONFIGURATION_ON ((u32)1 << IPTS_CONFIGURATION)
  3033. +#define IPTS_CALIBRATION_ON ((u32)1 << IPTS_CALIBRATION)
  3034. +#define IPTS_FEATURE_ON ((u32)1 << IPTS_FEATURE)
  3035. +
  3036. +// OpenCL kernel
  3037. +struct bin_workload {
  3038. + int cmdbuf_index;
  3039. + int iobuf_input;
  3040. + int iobuf_output[MAX_NUM_OUTPUT_BUFFERS];
  3041. +};
  3042. +
  3043. +struct bin_buffer {
  3044. + unsigned int handle;
  3045. + struct ipts_mapbuffer *buf;
  3046. +
  3047. + // only releasing vendor kernel unmaps output buffers
  3048. + bool no_unmap;
  3049. +};
  3050. +
  3051. +struct bin_alloc_info {
  3052. + struct bin_buffer *buffs;
  3053. + int num_of_allocations;
  3054. + int num_of_outputs;
  3055. +
  3056. + int num_of_buffers;
  3057. +};
  3058. +
  3059. +struct bin_guc_wq_item {
  3060. + unsigned int batch_offset;
  3061. + unsigned int size;
  3062. + char data[];
  3063. +};
  3064. +
  3065. +struct bin_kernel_info {
  3066. + struct bin_workload *wl;
  3067. + struct bin_alloc_info *alloc_info;
  3068. + struct bin_guc_wq_item *guc_wq_item;
  3069. + struct ipts_bin_bufid_patch bufid_patch;
  3070. +
  3071. + // 1: vendor, 0: postprocessing
  3072. + bool is_vendor;
  3073. +};
  3074. +
  3075. +struct bin_kernel_list {
  3076. + struct ipts_mapbuffer *bufid_buf;
  3077. + int num_of_kernels;
  3078. + struct bin_kernel_info kernels[];
  3079. +};
  3080. +
  3081. +struct bin_parse_info {
  3082. + u8 *data;
  3083. + int size;
  3084. + int parsed;
  3085. +
  3086. + struct ipts_bin_fw_info *fw_info;
  3087. +
  3088. + // only used by postprocessing
  3089. + struct bin_kernel_info *vendor_kernel;
  3090. +
  3091. + // interested vendor output index
  3092. + u32 interested_vendor_output;
  3093. +};
  3094. +
  3095. +static int bin_read_fw(struct ipts_info *ipts, const char *fw_name,
  3096. + u8 *data, int size)
  3097. +{
  3098. + const struct firmware *fw = NULL;
  3099. + int ret = 0;
  3100. +
  3101. + ret = ipts_request_firmware(&fw, fw_name, &ipts->cldev->dev);
  3102. + if (ret) {
  3103. + ipts_err(ipts, "cannot read fw %s\n", fw_name);
  3104. + return ret;
  3105. + }
  3106. +
  3107. + if (fw->size > size) {
  3108. + ipts_dbg(ipts, "too small buffer to contain fw data\n");
  3109. + ret = -EINVAL;
  3110. + } else {
  3111. + memcpy(data, fw->data, fw->size);
  3112. + }
  3113. +
  3114. + release_firmware(fw);
  3115. +
  3116. + return ret;
  3117. +}
  3118. +
  3119. +
  3120. +static struct ipts_bin_data_file_info *bin_get_data_file_info(
  3121. + struct ipts_bin_fw_info *fw_info, u32 io_buffer_type)
  3122. +{
  3123. + int i;
  3124. +
  3125. + for (i = 0; i < fw_info->num_of_data_files; i++) {
  3126. + if (fw_info->data_file[i].io_buffer_type == io_buffer_type)
  3127. + break;
  3128. + }
  3129. +
  3130. + if (i == fw_info->num_of_data_files)
  3131. + return NULL;
  3132. +
  3133. + return &fw_info->data_file[i];
  3134. +}
  3135. +
  3136. +static inline bool is_shared_data(
  3137. + const struct ipts_bin_data_file_info *data_file)
  3138. +{
  3139. + if (!data_file)
  3140. + return false;
  3141. +
  3142. + return (!!(data_file->flags & IPTS_DATA_FILE_FLAG_SHARE));
  3143. +}
  3144. +
  3145. +static inline bool is_alloc_cont_data(
  3146. + const struct ipts_bin_data_file_info *data_file)
  3147. +{
  3148. + if (!data_file)
  3149. + return false;
  3150. +
  3151. + return (!!(data_file->flags & IPTS_DATA_FILE_FLAG_ALLOC_CONTIGUOUS));
  3152. +}
  3153. +
  3154. +static inline bool is_parsing_vendor_kernel(
  3155. + const struct bin_parse_info *parse_info)
  3156. +{
  3157. + // vendor_kernel == null while loading itself
  3158. + return parse_info->vendor_kernel == NULL;
  3159. +}
  3160. +
  3161. +static int bin_read_allocation_list(struct ipts_info *ipts,
  3162. + struct bin_parse_info *parse_info,
  3163. + struct bin_alloc_info *alloc_info)
  3164. +{
  3165. + struct ipts_bin_alloc_list *alloc_list;
  3166. + int aidx, pidx, num_of_parallels, bidx, num_of_buffers;
  3167. + int parsed, size;
  3168. +
  3169. + parsed = parse_info->parsed;
  3170. + size = parse_info->size;
  3171. +
  3172. + alloc_list = (struct ipts_bin_alloc_list *)&parse_info->data[parsed];
  3173. +
  3174. + // validation check
  3175. + if (sizeof(alloc_list->num) > size - parsed)
  3176. + return -EINVAL;
  3177. +
  3178. + // read the number of aloocations
  3179. + parsed += sizeof(alloc_list->num);
  3180. +
  3181. + // validation check
  3182. + if (sizeof(alloc_list->alloc[0]) * alloc_list->num > size - parsed)
  3183. + return -EINVAL;
  3184. +
  3185. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  3186. + num_of_buffers = num_of_parallels * alloc_list->num + num_of_parallels;
  3187. + alloc_info->buffs = vmalloc(sizeof(struct bin_buffer) *
  3188. + num_of_buffers);
  3189. +
  3190. + if (alloc_info->buffs == NULL)
  3191. + return -ENOMEM;
  3192. +
  3193. + memset(alloc_info->buffs, 0, sizeof(struct bin_buffer) *
  3194. + num_of_buffers);
  3195. +
  3196. + for (aidx = 0; aidx < alloc_list->num; aidx++) {
  3197. + for (pidx = 0; pidx < num_of_parallels; pidx++) {
  3198. + bidx = aidx + (pidx * alloc_list->num);
  3199. + alloc_info->buffs[bidx].handle =
  3200. + alloc_list->alloc[aidx].handle;
  3201. + }
  3202. +
  3203. + parsed += sizeof(alloc_list->alloc[0]);
  3204. + }
  3205. +
  3206. + parse_info->parsed = parsed;
  3207. + alloc_info->num_of_allocations = alloc_list->num;
  3208. + alloc_info->num_of_buffers = num_of_buffers;
  3209. +
  3210. + ipts_dbg(ipts, "number of allocations = %d, buffers = %d\n",
  3211. + alloc_info->num_of_allocations,
  3212. + alloc_info->num_of_buffers);
  3213. +
  3214. + return 0;
  3215. +}
  3216. +
  3217. +static void patch_SBA(u32 *buf_addr, u64 gpu_addr, int size)
  3218. +{
  3219. + u64 *stateBase;
  3220. + u64 SBA;
  3221. + u32 inst;
  3222. + int i;
  3223. +
  3224. + SBA = gpu_addr + SBA_OFFSET_BYTES;
  3225. +
  3226. + for (i = 0; i < size / 4; i++) {
  3227. + inst = buf_addr[i];
  3228. + if (inst == BDW_SURFACE_BASE_ADDRESS) {
  3229. + stateBase = (u64 *)&buf_addr
  3230. + [i + SURFACE_STATE_OFFSET_WORD];
  3231. + *stateBase |= SBA;
  3232. + *stateBase |= 0x01; // enable
  3233. + break;
  3234. + }
  3235. + }
  3236. +}
  3237. +
  3238. +static int bin_read_cmd_buffer(struct ipts_info *ipts,
  3239. + struct bin_parse_info *parse_info,
  3240. + struct bin_alloc_info *alloc_info, struct bin_workload *wl)
  3241. +{
  3242. + struct ipts_bin_cmdbuf *cmd;
  3243. + struct ipts_mapbuffer *buf;
  3244. + int cidx, size, parsed, pidx, num_of_parallels;
  3245. +
  3246. + size = parse_info->size;
  3247. + parsed = parse_info->parsed;
  3248. +
  3249. + cmd = (struct ipts_bin_cmdbuf *)&parse_info->data[parsed];
  3250. +
  3251. + if (sizeof(cmd->size) > size - parsed)
  3252. + return -EINVAL;
  3253. +
  3254. + parsed += sizeof(cmd->size);
  3255. + if (cmd->size > size - parsed)
  3256. + return -EINVAL;
  3257. +
  3258. + ipts_dbg(ipts, "cmd buf size = %d\n", cmd->size);
  3259. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  3260. +
  3261. + // command buffers are located after the other allocations
  3262. + cidx = num_of_parallels * alloc_info->num_of_allocations;
  3263. + for (pidx = 0; pidx < num_of_parallels; pidx++) {
  3264. + buf = ipts_map_buffer(ipts, cmd->size, 0);
  3265. +
  3266. + if (buf == NULL)
  3267. + return -ENOMEM;
  3268. +
  3269. + ipts_dbg(ipts, "cmd_idx[%d] = %d, g:0x%p, c:0x%p\n", pidx,
  3270. + cidx, buf->gfx_addr, buf->cpu_addr);
  3271. +
  3272. + memcpy((void *)buf->cpu_addr, &(cmd->data[0]), cmd->size);
  3273. + patch_SBA(buf->cpu_addr, (u64)buf->gfx_addr, cmd->size);
  3274. +
  3275. + alloc_info->buffs[cidx].buf = buf;
  3276. + wl[pidx].cmdbuf_index = cidx;
  3277. + cidx++;
  3278. + }
  3279. +
  3280. + parsed += cmd->size;
  3281. + parse_info->parsed = parsed;
  3282. +
  3283. + return 0;
  3284. +}
  3285. +
  3286. +static int bin_find_alloc(struct ipts_info *ipts,
  3287. + struct bin_alloc_info *alloc_info, u32 handle)
  3288. +{
  3289. + int i;
  3290. +
  3291. + for (i = 0; i < alloc_info->num_of_allocations; i++) {
  3292. + if (alloc_info->buffs[i].handle == handle)
  3293. + return i;
  3294. + }
  3295. +
  3296. + return -1;
  3297. +}
  3298. +
  3299. +static struct ipts_mapbuffer *bin_get_vendor_kernel_output(
  3300. + struct bin_parse_info *parse_info, int pidx)
  3301. +{
  3302. + struct bin_kernel_info *vendor = parse_info->vendor_kernel;
  3303. + struct bin_alloc_info *alloc_info;
  3304. + int bidx, vidx;
  3305. +
  3306. + alloc_info = vendor->alloc_info;
  3307. + vidx = parse_info->interested_vendor_output;
  3308. +
  3309. + if (vidx >= alloc_info->num_of_outputs)
  3310. + return NULL;
  3311. +
  3312. + bidx = vendor->wl[pidx].iobuf_output[vidx];
  3313. +
  3314. + return alloc_info->buffs[bidx].buf;
  3315. +}
  3316. +
  3317. +static int bin_read_res_list(struct ipts_info *ipts,
  3318. + struct bin_parse_info *parse_info,
  3319. + struct bin_alloc_info *alloc_info, struct bin_workload *wl)
  3320. +{
  3321. + struct ipts_bin_res_list *res_list;
  3322. + struct ipts_bin_res *res;
  3323. + struct ipts_mapbuffer *buf;
  3324. + struct ipts_bin_data_file_info *data_file;
  3325. + u8 *bin_data;
  3326. + int i, size, parsed, pidx, num_of_parallels, oidx = -1;
  3327. + int bidx, num_of_alloc;
  3328. + u32 buf_size, flags, io_buf_type;
  3329. + bool initialize;
  3330. +
  3331. + parsed = parse_info->parsed;
  3332. + size = parse_info->size;
  3333. + bin_data = parse_info->data;
  3334. +
  3335. + res_list = (struct ipts_bin_res_list *)&parse_info->data[parsed];
  3336. +
  3337. + if (sizeof(res_list->num) > (size - parsed))
  3338. + return -EINVAL;
  3339. +
  3340. + parsed += sizeof(res_list->num);
  3341. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  3342. +
  3343. + ipts_dbg(ipts, "number of resources %u\n", res_list->num);
  3344. +
  3345. + for (i = 0; i < res_list->num; i++) {
  3346. + struct ipts_bin_io_header *io_hdr;
  3347. +
  3348. + initialize = false;
  3349. + io_buf_type = 0;
  3350. + flags = 0;
  3351. +
  3352. + // initial data
  3353. + data_file = NULL;
  3354. +
  3355. + res = (struct ipts_bin_res *)(&(bin_data[parsed]));
  3356. + if (sizeof(res[0]) > (size - parsed))
  3357. + return -EINVAL;
  3358. +
  3359. + ipts_dbg(ipts, "Resource(%d): handle 0x%08x type %u init %u size %u alsigned %u\n",
  3360. + i, res->handle, res->type, res->initialize,
  3361. + res->size, res->aligned_size);
  3362. +
  3363. + parsed += sizeof(res[0]);
  3364. +
  3365. + if (res->initialize) {
  3366. + if (res->size > (size - parsed))
  3367. + return -EINVAL;
  3368. + parsed += res->size;
  3369. + }
  3370. +
  3371. + initialize = res->initialize;
  3372. + if (!initialize || res->size <=
  3373. + sizeof(struct ipts_bin_io_header))
  3374. + goto read_res_list_no_init;
  3375. +
  3376. + io_hdr = (struct ipts_bin_io_header *)(&res->data[0]);
  3377. +
  3378. + if (strncmp(io_hdr->str, "INTELTOUCH", 10) != 0)
  3379. + goto read_res_list_no_init;
  3380. +
  3381. + data_file = bin_get_data_file_info(parse_info->fw_info,
  3382. + (u32)io_hdr->type);
  3383. +
  3384. + switch (io_hdr->type) {
  3385. + case IPTS_INPUT: {
  3386. + ipts_dbg(ipts, "input detected\n");
  3387. + io_buf_type = IPTS_INPUT_ON;
  3388. + flags = IPTS_BUF_FLAG_CONTIGUOUS;
  3389. + break;
  3390. + }
  3391. + case IPTS_OUTPUT: {
  3392. + ipts_dbg(ipts, "output detected\n");
  3393. + io_buf_type = IPTS_OUTPUT_ON;
  3394. + oidx++;
  3395. + break;
  3396. + }
  3397. + default: {
  3398. + if ((u32)io_hdr->type > 31) {
  3399. + ipts_err(ipts, "invalid io buffer : %u\n",
  3400. + (u32)io_hdr->type);
  3401. + continue;
  3402. + }
  3403. +
  3404. + if (is_alloc_cont_data(data_file))
  3405. + flags = IPTS_BUF_FLAG_CONTIGUOUS;
  3406. +
  3407. + io_buf_type = ((u32)1 << (u32)io_hdr->type);
  3408. + ipts_dbg(ipts, "special io buffer %u\n",
  3409. + io_hdr->type);
  3410. +
  3411. + break;
  3412. + }
  3413. + }
  3414. +
  3415. + initialize = false;
  3416. +
  3417. +read_res_list_no_init:
  3418. + num_of_alloc = alloc_info->num_of_allocations;
  3419. + bidx = bin_find_alloc(ipts, alloc_info, res->handle);
  3420. +
  3421. + if (bidx == -1) {
  3422. + ipts_dbg(ipts, "cannot find alloc info\n");
  3423. + return -EINVAL;
  3424. + }
  3425. +
  3426. + for (pidx = 0; pidx < num_of_parallels; pidx++,
  3427. + bidx += num_of_alloc) {
  3428. + if (!res->aligned_size)
  3429. + continue;
  3430. +
  3431. + if (!(pidx == 0 || (io_buf_type &&
  3432. + !is_shared_data(data_file))))
  3433. + continue;
  3434. +
  3435. + buf_size = res->aligned_size;
  3436. + if (io_buf_type & IPTS_INPUT_ON) {
  3437. + buf_size = max_t(u32, buf_size,
  3438. + ipts->device_info.frame_size);
  3439. +
  3440. + wl[pidx].iobuf_input = bidx;
  3441. + } else if (io_buf_type & IPTS_OUTPUT_ON) {
  3442. + wl[pidx].iobuf_output[oidx] = bidx;
  3443. +
  3444. + if (is_parsing_vendor_kernel(parse_info) ||
  3445. + oidx == 0)
  3446. + goto read_res_list_no_inout_err;
  3447. +
  3448. + ipts_err(ipts, "postproc with >1 inout is not supported: %d\n",
  3449. + oidx);
  3450. +
  3451. + return -EINVAL;
  3452. + }
  3453. +
  3454. +read_res_list_no_inout_err:
  3455. + if (!is_parsing_vendor_kernel(parse_info) &&
  3456. + io_buf_type & IPTS_OUTPUT_ON) {
  3457. + buf = bin_get_vendor_kernel_output(
  3458. + parse_info, pidx);
  3459. +
  3460. + alloc_info->buffs[bidx].no_unmap = true;
  3461. + } else {
  3462. + buf = ipts_map_buffer(ipts, buf_size, flags);
  3463. + }
  3464. +
  3465. + if (buf == NULL) {
  3466. + ipts_dbg(ipts, "ipts_map_buffer failed\n");
  3467. + return -ENOMEM;
  3468. + }
  3469. +
  3470. + if (initialize) {
  3471. + memcpy((void *)buf->cpu_addr, &(res->data[0]),
  3472. + res->size);
  3473. + } else if (data_file && strlen(data_file->file_name)) {
  3474. + bin_read_fw(ipts, data_file->file_name,
  3475. + buf->cpu_addr, buf_size);
  3476. + } else if (is_parsing_vendor_kernel(parse_info) ||
  3477. + !(io_buf_type & IPTS_OUTPUT_ON)) {
  3478. + memset((void *)buf->cpu_addr, 0, res->size);
  3479. + }
  3480. +
  3481. + alloc_info->buffs[bidx].buf = buf;
  3482. + }
  3483. + }
  3484. +
  3485. + alloc_info->num_of_outputs = oidx + 1;
  3486. + parse_info->parsed = parsed;
  3487. +
  3488. + return 0;
  3489. +}
  3490. +
  3491. +static int bin_read_patch_list(struct ipts_info *ipts,
  3492. + struct bin_parse_info *parse_info,
  3493. + struct bin_alloc_info *alloc_info, struct bin_workload *wl)
  3494. +{
  3495. + struct ipts_bin_patch_list *patch_list;
  3496. + struct ipts_bin_patch *patch;
  3497. + struct ipts_mapbuffer *cmd = NULL;
  3498. + u8 *batch;
  3499. + int parsed, size, i, pidx, num_of_parallels, cidx, bidx;
  3500. + unsigned int gtt_offset;
  3501. +
  3502. + parsed = parse_info->parsed;
  3503. + size = parse_info->size;
  3504. + patch_list = (struct ipts_bin_patch_list *)&parse_info->data[parsed];
  3505. +
  3506. + if (sizeof(patch_list->num) > (size - parsed))
  3507. + return -EFAULT;
  3508. + parsed += sizeof(patch_list->num);
  3509. +
  3510. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  3511. + patch = (struct ipts_bin_patch *)(&patch_list->patch[0]);
  3512. +
  3513. + for (i = 0; i < patch_list->num; i++) {
  3514. + if (sizeof(patch_list->patch[0]) > (size - parsed))
  3515. + return -EFAULT;
  3516. +
  3517. + for (pidx = 0; pidx < num_of_parallels; pidx++) {
  3518. + cidx = wl[pidx].cmdbuf_index;
  3519. + bidx = patch[i].index + pidx *
  3520. + alloc_info->num_of_allocations;
  3521. +
  3522. + // buffer is shared
  3523. + if (alloc_info->buffs[bidx].buf == NULL)
  3524. + bidx = patch[i].index;
  3525. +
  3526. + cmd = alloc_info->buffs[cidx].buf;
  3527. + batch = (char *)(u64)cmd->cpu_addr;
  3528. +
  3529. + gtt_offset = 0;
  3530. + if (alloc_info->buffs[bidx].buf != NULL) {
  3531. + gtt_offset = (u32)(u64)alloc_info->buffs
  3532. + [bidx].buf->gfx_addr;
  3533. + }
  3534. + gtt_offset += patch[i].alloc_offset;
  3535. +
  3536. + batch += patch[i].patch_offset;
  3537. + *(u32 *)batch = gtt_offset;
  3538. + }
  3539. +
  3540. + parsed += sizeof(patch_list->patch[0]);
  3541. + }
  3542. +
  3543. + parse_info->parsed = parsed;
  3544. +
  3545. + return 0;
  3546. +}
  3547. +
  3548. +static int bin_read_guc_wq_item(struct ipts_info *ipts,
  3549. + struct bin_parse_info *parse_info,
  3550. + struct bin_guc_wq_item **guc_wq_item)
  3551. +{
  3552. + struct ipts_bin_guc_wq_info *bin_guc_wq;
  3553. + struct bin_guc_wq_item *item;
  3554. + u8 *wi_data;
  3555. + int size, parsed, hdr_size, wi_size;
  3556. + int i, batch_offset;
  3557. +
  3558. + parsed = parse_info->parsed;
  3559. + size = parse_info->size;
  3560. + bin_guc_wq = (struct ipts_bin_guc_wq_info *)&parse_info->data[parsed];
  3561. +
  3562. + wi_size = bin_guc_wq->size;
  3563. + wi_data = bin_guc_wq->data;
  3564. + batch_offset = bin_guc_wq->batch_offset;
  3565. +
  3566. + ipts_dbg(ipts, "wi size = %d, bt offset = %d\n", wi_size, batch_offset);
  3567. +
  3568. + for (i = 0; i < wi_size / sizeof(u32); i++)
  3569. + ipts_dbg(ipts, "wi[%d] = 0x%08x\n", i, *((u32 *)wi_data + i));
  3570. +
  3571. + hdr_size = sizeof(bin_guc_wq->size) + sizeof(bin_guc_wq->batch_offset);
  3572. +
  3573. + if (hdr_size > (size - parsed))
  3574. + return -EINVAL;
  3575. +
  3576. + parsed += hdr_size;
  3577. + item = vmalloc(sizeof(struct bin_guc_wq_item) + wi_size);
  3578. +
  3579. + if (item == NULL)
  3580. + return -ENOMEM;
  3581. +
  3582. + item->size = wi_size;
  3583. + item->batch_offset = batch_offset;
  3584. + memcpy(item->data, wi_data, wi_size);
  3585. +
  3586. + *guc_wq_item = item;
  3587. +
  3588. + parsed += wi_size;
  3589. + parse_info->parsed = parsed;
  3590. +
  3591. + return 0;
  3592. +}
  3593. +
  3594. +static int bin_setup_guc_workqueue(struct ipts_info *ipts,
  3595. + struct bin_kernel_list *kernel_list)
  3596. +{
  3597. + struct bin_alloc_info *alloc_info;
  3598. + struct bin_workload *wl;
  3599. + struct bin_kernel_info *kernel;
  3600. + struct bin_buffer *bin_buf;
  3601. + u8 *wq_start, *wq_addr, *wi_data;
  3602. + int wq_size, wi_size, pidx, cidx, kidx, iter_size;
  3603. + int i, num_of_parallels, batch_offset, k_num, total_workload;
  3604. +
  3605. + wq_addr = (u8 *)ipts->resource.wq_info.wq_addr;
  3606. + wq_size = ipts->resource.wq_info.wq_size;
  3607. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  3608. + total_workload = ipts_get_wq_item_size(ipts);
  3609. + k_num = kernel_list->num_of_kernels;
  3610. +
  3611. + iter_size = total_workload * num_of_parallels;
  3612. + if (wq_size % iter_size) {
  3613. + ipts_err(ipts, "wq item cannot fit into wq\n");
  3614. + return -EINVAL;
  3615. + }
  3616. +
  3617. + wq_start = wq_addr;
  3618. + for (pidx = 0; pidx < num_of_parallels; pidx++) {
  3619. + kernel = &kernel_list->kernels[0];
  3620. +
  3621. + for (kidx = 0; kidx < k_num; kidx++, kernel++) {
  3622. + wl = kernel->wl;
  3623. + alloc_info = kernel->alloc_info;
  3624. +
  3625. + batch_offset = kernel->guc_wq_item->batch_offset;
  3626. + wi_size = kernel->guc_wq_item->size;
  3627. + wi_data = &kernel->guc_wq_item->data[0];
  3628. +
  3629. + cidx = wl[pidx].cmdbuf_index;
  3630. + bin_buf = &alloc_info->buffs[cidx];
  3631. +
  3632. + // Patch the WQ Data with proper batch buffer offset
  3633. + *(u32 *)(wi_data + batch_offset) =
  3634. + (u32)(unsigned long)(bin_buf->buf->gfx_addr);
  3635. +
  3636. + memcpy(wq_addr, wi_data, wi_size);
  3637. + wq_addr += wi_size;
  3638. + }
  3639. + }
  3640. +
  3641. + for (i = 0; i < (wq_size / iter_size) - 1; i++) {
  3642. + memcpy(wq_addr, wq_start, iter_size);
  3643. + wq_addr += iter_size;
  3644. + }
  3645. +
  3646. + return 0;
  3647. +}
  3648. +
  3649. +static int bin_read_bufid_patch(struct ipts_info *ipts,
  3650. + struct bin_parse_info *parse_info,
  3651. + struct ipts_bin_bufid_patch *bufid_patch)
  3652. +{
  3653. + struct ipts_bin_bufid_patch *patch;
  3654. + int size, parsed;
  3655. +
  3656. + parsed = parse_info->parsed;
  3657. + size = parse_info->size;
  3658. + patch = (struct ipts_bin_bufid_patch *)&parse_info->data[parsed];
  3659. +
  3660. + if (sizeof(struct ipts_bin_bufid_patch) > (size - parsed)) {
  3661. + ipts_dbg(ipts, "invalid bufid info\n");
  3662. + return -EINVAL;
  3663. + }
  3664. +
  3665. + parsed += sizeof(struct ipts_bin_bufid_patch);
  3666. + parse_info->parsed = parsed;
  3667. +
  3668. + memcpy(bufid_patch, patch, sizeof(struct ipts_bin_bufid_patch));
  3669. +
  3670. + return 0;
  3671. +}
  3672. +
  3673. +static int bin_setup_bufid_buffer(struct ipts_info *ipts,
  3674. + struct bin_kernel_list *kernel_list)
  3675. +{
  3676. + struct ipts_mapbuffer *buf, *cmd_buf;
  3677. + struct bin_kernel_info *last_kernel;
  3678. + struct bin_alloc_info *alloc_info;
  3679. + struct bin_workload *wl;
  3680. + u8 *batch;
  3681. + int pidx, num_of_parallels, cidx;
  3682. + u32 mem_offset, imm_offset;
  3683. +
  3684. + buf = ipts_map_buffer(ipts, PAGE_SIZE, 0);
  3685. + if (!buf)
  3686. + return -ENOMEM;
  3687. +
  3688. + last_kernel = &kernel_list->kernels[kernel_list->num_of_kernels - 1];
  3689. +
  3690. + mem_offset = last_kernel->bufid_patch.mem_offset;
  3691. + imm_offset = last_kernel->bufid_patch.imm_offset;
  3692. + wl = last_kernel->wl;
  3693. + alloc_info = last_kernel->alloc_info;
  3694. +
  3695. + // Initialize the buffer with default value
  3696. + *((u32 *)buf->cpu_addr) = LASTSUBMITID_DEFAULT_VALUE;
  3697. + ipts->current_buffer_index = LASTSUBMITID_DEFAULT_VALUE;
  3698. + ipts->last_buffer_completed = LASTSUBMITID_DEFAULT_VALUE;
  3699. + ipts->last_submitted_id = (int *)buf->cpu_addr;
  3700. +
  3701. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  3702. +
  3703. + for (pidx = 0; pidx < num_of_parallels; pidx++) {
  3704. + cidx = wl[pidx].cmdbuf_index;
  3705. + cmd_buf = alloc_info->buffs[cidx].buf;
  3706. + batch = (u8 *)(u64)cmd_buf->cpu_addr;
  3707. +
  3708. + *((u32 *)(batch + mem_offset)) = (u32)(u64)(buf->gfx_addr);
  3709. + *((u32 *)(batch + imm_offset)) = pidx;
  3710. + }
  3711. +
  3712. + kernel_list->bufid_buf = buf;
  3713. +
  3714. + return 0;
  3715. +}
  3716. +
  3717. +static void unmap_buffers(struct ipts_info *ipts,
  3718. + struct bin_alloc_info *alloc_info)
  3719. +{
  3720. + struct bin_buffer *buffs;
  3721. + int i, num_of_buffers;
  3722. +
  3723. + num_of_buffers = alloc_info->num_of_buffers;
  3724. + buffs = &alloc_info->buffs[0];
  3725. +
  3726. + for (i = 0; i < num_of_buffers; i++) {
  3727. + if (buffs[i].no_unmap != true && buffs[i].buf != NULL)
  3728. + ipts_unmap_buffer(ipts, buffs[i].buf);
  3729. + }
  3730. +}
  3731. +
  3732. +static int load_kernel(struct ipts_info *ipts,
  3733. + struct bin_parse_info *parse_info,
  3734. + struct bin_kernel_info *kernel)
  3735. +{
  3736. + struct ipts_bin_header *hdr;
  3737. + struct bin_workload *wl;
  3738. + struct bin_alloc_info *alloc_info;
  3739. + struct bin_guc_wq_item *guc_wq_item = NULL;
  3740. + struct ipts_bin_bufid_patch bufid_patch;
  3741. + int num_of_parallels, ret;
  3742. +
  3743. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  3744. +
  3745. + // check header version and magic numbers
  3746. + hdr = (struct ipts_bin_header *)parse_info->data;
  3747. + if (hdr->version != IPTS_BIN_HEADER_VERSION ||
  3748. + strncmp(hdr->str, "IOCL", 4) != 0) {
  3749. + ipts_err(ipts, "binary header is not correct version = %d, ",
  3750. + hdr->version);
  3751. +
  3752. + ipts_err(ipts, "string = %c%c%c%c\n", hdr->str[0], hdr->str[1],
  3753. + hdr->str[2], hdr->str[3]);
  3754. +
  3755. + return -EINVAL;
  3756. + }
  3757. +
  3758. + parse_info->parsed = sizeof(struct ipts_bin_header);
  3759. + wl = vmalloc(sizeof(struct bin_workload) * num_of_parallels);
  3760. +
  3761. + if (wl == NULL)
  3762. + return -ENOMEM;
  3763. +
  3764. + memset(wl, 0, sizeof(struct bin_workload) * num_of_parallels);
  3765. + alloc_info = vmalloc(sizeof(struct bin_alloc_info));
  3766. +
  3767. + if (alloc_info == NULL) {
  3768. + vfree(wl);
  3769. + return -ENOMEM;
  3770. + }
  3771. +
  3772. + memset(alloc_info, 0, sizeof(struct bin_alloc_info));
  3773. +
  3774. + ipts_dbg(ipts, "kernel setup(size : %d)\n", parse_info->size);
  3775. +
  3776. + ret = bin_read_allocation_list(ipts, parse_info, alloc_info);
  3777. + if (ret) {
  3778. + ipts_dbg(ipts, "error read_allocation_list\n");
  3779. + goto setup_error;
  3780. + }
  3781. +
  3782. + ret = bin_read_cmd_buffer(ipts, parse_info, alloc_info, wl);
  3783. + if (ret) {
  3784. + ipts_dbg(ipts, "error read_cmd_buffer\n");
  3785. + goto setup_error;
  3786. + }
  3787. +
  3788. + ret = bin_read_res_list(ipts, parse_info, alloc_info, wl);
  3789. + if (ret) {
  3790. + ipts_dbg(ipts, "error read_res_list\n");
  3791. + goto setup_error;
  3792. + }
  3793. +
  3794. + ret = bin_read_patch_list(ipts, parse_info, alloc_info, wl);
  3795. + if (ret) {
  3796. + ipts_dbg(ipts, "error read_patch_list\n");
  3797. + goto setup_error;
  3798. + }
  3799. +
  3800. + ret = bin_read_guc_wq_item(ipts, parse_info, &guc_wq_item);
  3801. + if (ret) {
  3802. + ipts_dbg(ipts, "error read_guc_workqueue\n");
  3803. + goto setup_error;
  3804. + }
  3805. +
  3806. + memset(&bufid_patch, 0, sizeof(bufid_patch));
  3807. +
  3808. + ret = bin_read_bufid_patch(ipts, parse_info, &bufid_patch);
  3809. + if (ret) {
  3810. + ipts_dbg(ipts, "error read_bufid_patch\n");
  3811. + goto setup_error;
  3812. + }
  3813. +
  3814. + kernel->wl = wl;
  3815. + kernel->alloc_info = alloc_info;
  3816. + kernel->is_vendor = is_parsing_vendor_kernel(parse_info);
  3817. + kernel->guc_wq_item = guc_wq_item;
  3818. +
  3819. + memcpy(&kernel->bufid_patch, &bufid_patch, sizeof(bufid_patch));
  3820. +
  3821. + return 0;
  3822. +
  3823. +setup_error:
  3824. + vfree(guc_wq_item);
  3825. +
  3826. + unmap_buffers(ipts, alloc_info);
  3827. +
  3828. + vfree(alloc_info->buffs);
  3829. + vfree(alloc_info);
  3830. + vfree(wl);
  3831. +
  3832. + return ret;
  3833. +}
  3834. +
  3835. +void bin_setup_input_output(struct ipts_info *ipts,
  3836. + struct bin_kernel_list *kernel_list)
  3837. +{
  3838. + struct bin_kernel_info *vendor_kernel;
  3839. + struct bin_workload *wl;
  3840. + struct ipts_mapbuffer *buf;
  3841. + struct bin_alloc_info *alloc_info;
  3842. + int pidx, num_of_parallels, i, bidx;
  3843. +
  3844. + vendor_kernel = &kernel_list->kernels[0];
  3845. +
  3846. + wl = vendor_kernel->wl;
  3847. + alloc_info = vendor_kernel->alloc_info;
  3848. + ipts->resource.num_of_outputs = alloc_info->num_of_outputs;
  3849. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  3850. +
  3851. + for (pidx = 0; pidx < num_of_parallels; pidx++) {
  3852. + bidx = wl[pidx].iobuf_input;
  3853. + buf = alloc_info->buffs[bidx].buf;
  3854. +
  3855. + ipts_dbg(ipts, "in_buf[%d](%d) c:%p, p:%p, g:%p\n",
  3856. + pidx, bidx, (void *)buf->cpu_addr,
  3857. + (void *)buf->phy_addr, (void *)buf->gfx_addr);
  3858. +
  3859. + ipts_set_input_buffer(ipts, pidx, buf->cpu_addr, buf->phy_addr);
  3860. +
  3861. + for (i = 0; i < alloc_info->num_of_outputs; i++) {
  3862. + bidx = wl[pidx].iobuf_output[i];
  3863. + buf = alloc_info->buffs[bidx].buf;
  3864. +
  3865. + ipts_dbg(ipts, "out_buf[%d][%d] c:%p, p:%p, g:%p\n",
  3866. + pidx, i, (void *)buf->cpu_addr,
  3867. + (void *)buf->phy_addr, (void *)buf->gfx_addr);
  3868. +
  3869. + ipts_set_output_buffer(ipts, pidx, i,
  3870. + buf->cpu_addr, buf->phy_addr);
  3871. + }
  3872. + }
  3873. +}
  3874. +
  3875. +static void unload_kernel(struct ipts_info *ipts,
  3876. + struct bin_kernel_info *kernel)
  3877. +{
  3878. + struct bin_alloc_info *alloc_info = kernel->alloc_info;
  3879. + struct bin_guc_wq_item *guc_wq_item = kernel->guc_wq_item;
  3880. +
  3881. + if (guc_wq_item)
  3882. + vfree(guc_wq_item);
  3883. +
  3884. + if (alloc_info) {
  3885. + unmap_buffers(ipts, alloc_info);
  3886. +
  3887. + vfree(alloc_info->buffs);
  3888. + vfree(alloc_info);
  3889. + }
  3890. +}
  3891. +
  3892. +static int setup_kernel(struct ipts_info *ipts,
  3893. + struct ipts_bin_fw_list *fw_list)
  3894. +{
  3895. + struct bin_kernel_list *kernel_list = NULL;
  3896. + struct bin_kernel_info *kernel = NULL;
  3897. + const struct firmware *fw = NULL;
  3898. + struct bin_workload *wl;
  3899. + struct ipts_bin_fw_info *fw_info;
  3900. + char *fw_name, *fw_data;
  3901. + struct bin_parse_info parse_info;
  3902. + int ret = 0, kidx = 0, num_of_kernels = 0;
  3903. + int vidx, total_workload = 0;
  3904. +
  3905. + num_of_kernels = fw_list->num_of_fws;
  3906. + kernel_list = vmalloc(sizeof(*kernel) *
  3907. + num_of_kernels + sizeof(*kernel_list));
  3908. +
  3909. + if (kernel_list == NULL)
  3910. + return -ENOMEM;
  3911. +
  3912. + memset(kernel_list, 0, sizeof(*kernel) *
  3913. + num_of_kernels + sizeof(*kernel_list));
  3914. +
  3915. + kernel_list->num_of_kernels = num_of_kernels;
  3916. + kernel = &kernel_list->kernels[0];
  3917. +
  3918. + fw_data = (char *)&fw_list->fw_info[0];
  3919. + for (kidx = 0; kidx < num_of_kernels; kidx++) {
  3920. + fw_info = (struct ipts_bin_fw_info *)fw_data;
  3921. + fw_name = &fw_info->fw_name[0];
  3922. + vidx = fw_info->vendor_output;
  3923. +
  3924. + ret = ipts_request_firmware(&fw, fw_name, &ipts->cldev->dev);
  3925. + if (ret) {
  3926. + ipts_err(ipts, "cannot read fw %s\n", fw_name);
  3927. + goto error_exit;
  3928. + }
  3929. +
  3930. + parse_info.data = (u8 *)fw->data;
  3931. + parse_info.size = fw->size;
  3932. + parse_info.parsed = 0;
  3933. + parse_info.fw_info = fw_info;
  3934. + parse_info.vendor_kernel = (kidx == 0) ? NULL : &kernel[0];
  3935. + parse_info.interested_vendor_output = vidx;
  3936. +
  3937. + ret = load_kernel(ipts, &parse_info, &kernel[kidx]);
  3938. + if (ret) {
  3939. + ipts_err(ipts, "do_setup_kernel error : %d\n", ret);
  3940. + release_firmware(fw);
  3941. + goto error_exit;
  3942. + }
  3943. +
  3944. + release_firmware(fw);
  3945. +
  3946. + total_workload += kernel[kidx].guc_wq_item->size;
  3947. +
  3948. + // advance to the next kernel
  3949. + fw_data += sizeof(struct ipts_bin_fw_info);
  3950. + fw_data += sizeof(struct ipts_bin_data_file_info) *
  3951. + fw_info->num_of_data_files;
  3952. + }
  3953. +
  3954. + ipts_set_wq_item_size(ipts, total_workload);
  3955. +
  3956. + ret = bin_setup_guc_workqueue(ipts, kernel_list);
  3957. + if (ret) {
  3958. + ipts_dbg(ipts, "error setup_guc_workqueue\n");
  3959. + goto error_exit;
  3960. + }
  3961. +
  3962. + ret = bin_setup_bufid_buffer(ipts, kernel_list);
  3963. + if (ret) {
  3964. + ipts_dbg(ipts, "error setup_lastbubmit_buffer\n");
  3965. + goto error_exit;
  3966. + }
  3967. +
  3968. + bin_setup_input_output(ipts, kernel_list);
  3969. +
  3970. + // workload is not needed during run-time so free them
  3971. + for (kidx = 0; kidx < num_of_kernels; kidx++) {
  3972. + wl = kernel[kidx].wl;
  3973. + vfree(wl);
  3974. + }
  3975. +
  3976. + ipts->kernel_handle = (u64)kernel_list;
  3977. +
  3978. + return 0;
  3979. +
  3980. +error_exit:
  3981. +
  3982. + for (kidx = 0; kidx < num_of_kernels; kidx++) {
  3983. + wl = kernel[kidx].wl;
  3984. + vfree(wl);
  3985. + unload_kernel(ipts, &kernel[kidx]);
  3986. + }
  3987. +
  3988. + vfree(kernel_list);
  3989. +
  3990. + return ret;
  3991. +}
  3992. +
  3993. +
  3994. +static void release_kernel(struct ipts_info *ipts)
  3995. +{
  3996. + struct bin_kernel_list *kernel_list;
  3997. + struct bin_kernel_info *kernel;
  3998. + int kidx, knum;
  3999. +
  4000. + kernel_list = (struct bin_kernel_list *)ipts->kernel_handle;
  4001. + knum = kernel_list->num_of_kernels;
  4002. + kernel = &kernel_list->kernels[0];
  4003. +
  4004. + for (kidx = 0; kidx < knum; kidx++) {
  4005. + unload_kernel(ipts, kernel);
  4006. + kernel++;
  4007. + }
  4008. +
  4009. + ipts_unmap_buffer(ipts, kernel_list->bufid_buf);
  4010. +
  4011. + vfree(kernel_list);
  4012. + ipts->kernel_handle = 0;
  4013. +}
  4014. +
  4015. +int ipts_init_kernels(struct ipts_info *ipts)
  4016. +{
  4017. + struct ipts_bin_fw_list *fw_list;
  4018. + int ret;
  4019. +
  4020. + ret = ipts_open_gpu(ipts);
  4021. + if (ret) {
  4022. + ipts_err(ipts, "open gpu error : %d\n", ret);
  4023. + return ret;
  4024. + }
  4025. +
  4026. + ret = ipts_request_firmware_config(ipts, &fw_list);
  4027. + if (ret) {
  4028. + ipts_err(ipts, "request firmware config error : %d\n", ret);
  4029. + goto close_gpu;
  4030. + }
  4031. +
  4032. + ret = setup_kernel(ipts, fw_list);
  4033. + if (ret) {
  4034. + ipts_err(ipts, "setup kernel error : %d\n", ret);
  4035. + goto close_gpu;
  4036. + }
  4037. +
  4038. + return ret;
  4039. +
  4040. +close_gpu:
  4041. + ipts_close_gpu(ipts);
  4042. +
  4043. + return ret;
  4044. +}
  4045. +
  4046. +void ipts_release_kernels(struct ipts_info *ipts)
  4047. +{
  4048. + release_kernel(ipts);
  4049. + ipts_close_gpu(ipts);
  4050. +}
  4051. diff --git a/drivers/misc/ipts/kernel.h b/drivers/misc/ipts/kernel.h
  4052. new file mode 100644
  4053. index 0000000000000..7be45da01cfc0
  4054. --- /dev/null
  4055. +++ b/drivers/misc/ipts/kernel.h
  4056. @@ -0,0 +1,17 @@
  4057. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  4058. +/*
  4059. + *
  4060. + * Intel Precise Touch & Stylus
  4061. + * Copyright (c) 2016 Intel Corporation
  4062. + *
  4063. + */
  4064. +
  4065. +#ifndef _IPTS_KERNEL_H_
  4066. +#define _IPTS_KERNEL_H_
  4067. +
  4068. +#include "ipts.h"
  4069. +
  4070. +int ipts_init_kernels(struct ipts_info *ipts);
  4071. +void ipts_release_kernels(struct ipts_info *ipts);
  4072. +
  4073. +#endif // _IPTS_KERNEL_H_
  4074. diff --git a/drivers/misc/ipts/mei-msgs.h b/drivers/misc/ipts/mei-msgs.h
  4075. new file mode 100644
  4076. index 0000000000000..036b74f7234ef
  4077. --- /dev/null
  4078. +++ b/drivers/misc/ipts/mei-msgs.h
  4079. @@ -0,0 +1,901 @@
  4080. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  4081. +/*
  4082. + *
  4083. + * Intel Precise Touch & Stylus
  4084. + * Copyright (c) 2013-2016 Intel Corporation
  4085. + *
  4086. + */
  4087. +
  4088. +#ifndef _IPTS_MEI_MSGS_H_
  4089. +#define _IPTS_MEI_MSGS_H_
  4090. +
  4091. +#include <linux/build_bug.h>
  4092. +
  4093. +#include "sensor-regs.h"
  4094. +
  4095. +#pragma pack(1)
  4096. +
  4097. +// Define static_assert macro (which will be available after 5.1
  4098. +// and not available on 4.19 yet) to check structure size and fail
  4099. +// compile for unexpected mismatch.
  4100. +// Taken from upstream commit 6bab69c65013bed5fce9f101a64a84d0385b3946.
  4101. +#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr)
  4102. +#define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
  4103. +
  4104. +// Initial protocol version
  4105. +#define TOUCH_HECI_CLIENT_PROTOCOL_VERSION 10
  4106. +
  4107. +// GUID that identifies the Touch HECI client.
  4108. +#define TOUCH_HECI_CLIENT_GUID \
  4109. + {0x3e8d0870, 0x271a, 0x4208, \
  4110. + {0x8e, 0xb5, 0x9a, 0xcb, 0x94, 0x02, 0xae, 0x04} }
  4111. +
  4112. +#define TOUCH_SENSOR_GET_DEVICE_INFO_CMD 0x00000001
  4113. +#define TOUCH_SENSOR_GET_DEVICE_INFO_RSP 0x80000001
  4114. +
  4115. +#define TOUCH_SENSOR_SET_MODE_CMD 0x00000002
  4116. +#define TOUCH_SENSOR_SET_MODE_RSP 0x80000002
  4117. +
  4118. +#define TOUCH_SENSOR_SET_MEM_WINDOW_CMD 0x00000003
  4119. +#define TOUCH_SENSOR_SET_MEM_WINDOW_RSP 0x80000003
  4120. +
  4121. +#define TOUCH_SENSOR_QUIESCE_IO_CMD 0x00000004
  4122. +#define TOUCH_SENSOR_QUIESCE_IO_RSP 0x80000004
  4123. +
  4124. +#define TOUCH_SENSOR_HID_READY_FOR_DATA_CMD 0x00000005
  4125. +#define TOUCH_SENSOR_HID_READY_FOR_DATA_RSP 0x80000005
  4126. +
  4127. +#define TOUCH_SENSOR_FEEDBACK_READY_CMD 0x00000006
  4128. +#define TOUCH_SENSOR_FEEDBACK_READY_RSP 0x80000006
  4129. +
  4130. +#define TOUCH_SENSOR_CLEAR_MEM_WINDOW_CMD 0x00000007
  4131. +#define TOUCH_SENSOR_CLEAR_MEM_WINDOW_RSP 0x80000007
  4132. +
  4133. +#define TOUCH_SENSOR_NOTIFY_DEV_READY_CMD 0x00000008
  4134. +#define TOUCH_SENSOR_NOTIFY_DEV_READY_RSP 0x80000008
  4135. +
  4136. +#define TOUCH_SENSOR_SET_POLICIES_CMD 0x00000009
  4137. +#define TOUCH_SENSOR_SET_POLICIES_RSP 0x80000009
  4138. +
  4139. +#define TOUCH_SENSOR_GET_POLICIES_CMD 0x0000000A
  4140. +#define TOUCH_SENSOR_GET_POLICIES_RSP 0x8000000A
  4141. +
  4142. +#define TOUCH_SENSOR_RESET_CMD 0x0000000B
  4143. +#define TOUCH_SENSOR_RESET_RSP 0x8000000B
  4144. +
  4145. +#define TOUCH_SENSOR_READ_ALL_REGS_CMD 0x0000000C
  4146. +#define TOUCH_SENSOR_READ_ALL_REGS_RSP 0x8000000C
  4147. +
  4148. +// ME sends this message to indicate previous command was unrecognized
  4149. +#define TOUCH_SENSOR_CMD_ERROR_RSP 0x8FFFFFFF
  4150. +
  4151. +#define TOUCH_SENSOR_MAX_DATA_BUFFERS 16
  4152. +#define TOUCH_HID_2_ME_BUFFER_ID TOUCH_SENSOR_MAX_DATA_BUFFERS
  4153. +#define TOUCH_HID_2_ME_BUFFER_SIZE_MAX 1024
  4154. +#define TOUCH_INVALID_BUFFER_ID 0xFF
  4155. +
  4156. +#define TOUCH_DEFAULT_DOZE_TIMER_SECONDS 30
  4157. +
  4158. +#define TOUCH_MSG_SIZE_MAX_BYTES \
  4159. + (MAX(sizeof(struct touch_sensor_msg_m2h), \
  4160. + sizeof(struct touch_sensor_msg_h2m)))
  4161. +
  4162. +// indicates GuC got reset and ME must re-read GuC data such as
  4163. +// TailOffset and Doorbell Cookie values
  4164. +#define TOUCH_SENSOR_QUIESCE_FLAG_GUC_RESET BIT(0)
  4165. +
  4166. +/*
  4167. + * Debug Policy bits used by TOUCH_POLICY_DATA.DebugOverride
  4168. + */
  4169. +
  4170. +// Disable sensor startup timer
  4171. +#define TOUCH_DBG_POLICY_OVERRIDE_STARTUP_TIMER_DIS BIT(0)
  4172. +
  4173. +// Disable Sync Byte check
  4174. +#define TOUCH_DBG_POLICY_OVERRIDE_SYNC_BYTE_DIS BIT(1)
  4175. +
  4176. +// Disable error resets
  4177. +#define TOUCH_DBG_POLICY_OVERRIDE_ERR_RESET_DIS BIT(2)
  4178. +
  4179. +/*
  4180. + * Touch Sensor Status Codes
  4181. + */
  4182. +enum touch_status {
  4183. + // Requested operation was successful
  4184. + TOUCH_STATUS_SUCCESS = 0,
  4185. +
  4186. + // Invalid parameter(s) sent
  4187. + TOUCH_STATUS_INVALID_PARAMS,
  4188. +
  4189. + // Unable to validate address range
  4190. + TOUCH_STATUS_ACCESS_DENIED,
  4191. +
  4192. + // HECI message incorrect size for specified command
  4193. + TOUCH_STATUS_CMD_SIZE_ERROR,
  4194. +
  4195. + // Memory window not set or device is not armed for operation
  4196. + TOUCH_STATUS_NOT_READY,
  4197. +
  4198. + // There is already an outstanding message of the same type, must
  4199. + // wait for response before sending another request of that type
  4200. + TOUCH_STATUS_REQUEST_OUTSTANDING,
  4201. +
  4202. + // Sensor could not be found. Either no sensor is connected,
  4203. + // the sensor has not yet initialized, or the system is
  4204. + // improperly configured.
  4205. + TOUCH_STATUS_NO_SENSOR_FOUND,
  4206. +
  4207. + // Not enough memory/storage for requested operation
  4208. + TOUCH_STATUS_OUT_OF_MEMORY,
  4209. +
  4210. + // Unexpected error occurred
  4211. + TOUCH_STATUS_INTERNAL_ERROR,
  4212. +
  4213. + // Used in TOUCH_SENSOR_HID_READY_FOR_DATA_RSP to indicate sensor
  4214. + // has been disabled or reset and must be reinitialized.
  4215. + TOUCH_STATUS_SENSOR_DISABLED,
  4216. +
  4217. + // Used to indicate compatibility revision check between sensor and ME
  4218. + // failed, or protocol ver between ME/HID/Kernels failed.
  4219. + TOUCH_STATUS_COMPAT_CHECK_FAIL,
  4220. +
  4221. + // Indicates sensor went through a reset initiated by ME
  4222. + TOUCH_STATUS_SENSOR_EXPECTED_RESET,
  4223. +
  4224. + // Indicates sensor went through an unexpected reset
  4225. + TOUCH_STATUS_SENSOR_UNEXPECTED_RESET,
  4226. +
  4227. + // Requested sensor reset failed to complete
  4228. + TOUCH_STATUS_RESET_FAILED,
  4229. +
  4230. + // Operation timed out
  4231. + TOUCH_STATUS_TIMEOUT,
  4232. +
  4233. + // Test mode pattern did not match expected values
  4234. + TOUCH_STATUS_TEST_MODE_FAIL,
  4235. +
  4236. + // Indicates sensor reported fatal error during reset sequence.
  4237. + // Further progress is not possible.
  4238. + TOUCH_STATUS_SENSOR_FAIL_FATAL,
  4239. +
  4240. + // Indicates sensor reported non-fatal error during reset sequence.
  4241. + // HID/BIOS logs error and attempts to continue.
  4242. + TOUCH_STATUS_SENSOR_FAIL_NONFATAL,
  4243. +
  4244. + // Indicates sensor reported invalid capabilities, such as not
  4245. + // supporting required minimum frequency or I/O mode.
  4246. + TOUCH_STATUS_INVALID_DEVICE_CAPS,
  4247. +
  4248. + // Indicates that command cannot be complete until ongoing Quiesce I/O
  4249. + // flow has completed.
  4250. + TOUCH_STATUS_QUIESCE_IO_IN_PROGRESS,
  4251. +
  4252. + // Invalid value, never returned
  4253. + TOUCH_STATUS_MAX
  4254. +};
  4255. +static_assert(sizeof(enum touch_status) == 4);
  4256. +
  4257. +/*
  4258. + * Defines for message structures used for Host to ME communication
  4259. + */
  4260. +enum touch_sensor_mode {
  4261. + // Set mode to HID mode
  4262. + TOUCH_SENSOR_MODE_HID = 0,
  4263. +
  4264. + // Set mode to Raw Data mode
  4265. + TOUCH_SENSOR_MODE_RAW_DATA,
  4266. +
  4267. + // Used like TOUCH_SENSOR_MODE_HID but data coming from sensor is
  4268. + // not necessarily a HID packet.
  4269. + TOUCH_SENSOR_MODE_SENSOR_DEBUG = 4,
  4270. +
  4271. + // Invalid value
  4272. + TOUCH_SENSOR_MODE_MAX
  4273. +};
  4274. +static_assert(sizeof(enum touch_sensor_mode) == 4);
  4275. +
  4276. +struct touch_sensor_set_mode_cmd_data {
  4277. + // Indicate desired sensor mode
  4278. + enum touch_sensor_mode sensor_mode;
  4279. +
  4280. + // For future expansion
  4281. + u32 Reserved[3];
  4282. +};
  4283. +static_assert(sizeof(struct touch_sensor_set_mode_cmd_data) == 16);
  4284. +
  4285. +struct touch_sensor_set_mem_window_cmd_data {
  4286. + // Lower 32 bits of Touch Data Buffer physical address. Size of each
  4287. + // buffer should be TOUCH_SENSOR_GET_DEVICE_INFO_RSP_DATA.FrameSize
  4288. + u32 touch_data_buffer_addr_lower[TOUCH_SENSOR_MAX_DATA_BUFFERS];
  4289. +
  4290. + // Upper 32 bits of Touch Data Buffer physical address. Size of each
  4291. + // buffer should be TOUCH_SENSOR_GET_DEVICE_INFO_RSP_DATA.FrameSize
  4292. + u32 touch_data_buffer_addr_upper[TOUCH_SENSOR_MAX_DATA_BUFFERS];
  4293. +
  4294. + // Lower 32 bits of Tail Offset physical address
  4295. + u32 tail_offset_addr_lower;
  4296. +
  4297. + // Upper 32 bits of Tail Offset physical address, always 32 bit,
  4298. + // increment by WorkQueueItemSize
  4299. + u32 tail_offset_addr_upper;
  4300. +
  4301. + // Lower 32 bits of Doorbell register physical address
  4302. + u32 doorbell_cookie_addr_lower;
  4303. +
  4304. + // Upper 32 bits of Doorbell register physical address, always 32 bit,
  4305. + // increment as integer, rollover to 1
  4306. + u32 doorbell_cookie_addr_upper;
  4307. +
  4308. + // Lower 32 bits of Feedback Buffer physical address. Size of each
  4309. + // buffer should be TOUCH_SENSOR_GET_DEVICE_INFO_RSP_DATA.FeedbackSize
  4310. + u32 feedback_buffer_addr_lower[TOUCH_SENSOR_MAX_DATA_BUFFERS];
  4311. +
  4312. + // Upper 32 bits of Feedback Buffer physical address. Size of each
  4313. + // buffer should be TOUCH_SENSOR_GET_DEVICE_INFO_RSP_DATA.FeedbackSize
  4314. + u32 feedback_buffer_addr_upper[TOUCH_SENSOR_MAX_DATA_BUFFERS];
  4315. +
  4316. + // Lower 32 bits of dedicated HID to ME communication buffer.
  4317. + // Size is Hid2MeBufferSize.
  4318. + u32 hid2me_buffer_addr_lower;
  4319. +
  4320. + // Upper 32 bits of dedicated HID to ME communication buffer.
  4321. + // Size is Hid2MeBufferSize.
  4322. + u32 hid2me_buffer_addr_upper;
  4323. +
  4324. + // Size in bytes of Hid2MeBuffer, can be no bigger than
  4325. + // TOUCH_HID_2_ME_BUFFER_SIZE_MAX
  4326. + u32 hid2me_buffer_size;
  4327. +
  4328. + // For future expansion
  4329. + u8 reserved1;
  4330. +
  4331. + // Size in bytes of the GuC Work Queue Item pointed to by TailOffset
  4332. + u8 work_queue_item_size;
  4333. +
  4334. + // Size in bytes of the entire GuC Work Queue
  4335. + u16 work_queue_size;
  4336. +
  4337. + // For future expansion
  4338. + u32 reserved[8];
  4339. +};
  4340. +static_assert(sizeof(struct touch_sensor_set_mem_window_cmd_data) == 320);
  4341. +
  4342. +struct touch_sensor_quiesce_io_cmd_data {
  4343. + // Optionally set TOUCH_SENSOR_QUIESCE_FLAG_GUC_RESET
  4344. + u32 quiesce_flags;
  4345. + u32 reserved[2];
  4346. +};
  4347. +static_assert(sizeof(struct touch_sensor_quiesce_io_cmd_data) == 12);
  4348. +
  4349. +struct touch_sensor_feedback_ready_cmd_data {
  4350. + // Index value from 0 to TOUCH_HID_2_ME_BUFFER_ID used to indicate
  4351. + // which Feedback Buffer to use. Using special value
  4352. + // TOUCH_HID_2_ME_BUFFER_ID is an indication to ME to
  4353. + // get feedback data from the Hid2Me buffer instead of one
  4354. + // of the standard Feedback buffers.
  4355. + u8 feedback_index;
  4356. +
  4357. + // For future expansion
  4358. + u8 reserved1[3];
  4359. +
  4360. + // Transaction ID that was originally passed to host in
  4361. + // TOUCH_HID_PRIVATE_DATA. Used to track round trip of a given
  4362. + // transaction for performance measurements.
  4363. + u32 transaction_id;
  4364. +
  4365. + // For future expansion
  4366. + u32 reserved2[2];
  4367. +};
  4368. +static_assert(sizeof(struct touch_sensor_feedback_ready_cmd_data) == 16);
  4369. +
  4370. +enum touch_freq_override {
  4371. + // Do not apply any override
  4372. + TOUCH_FREQ_OVERRIDE_NONE,
  4373. +
  4374. + // Force frequency to 10MHz (not currently supported)
  4375. + TOUCH_FREQ_OVERRIDE_10MHZ,
  4376. +
  4377. + // Force frequency to 17MHz
  4378. + TOUCH_FREQ_OVERRIDE_17MHZ,
  4379. +
  4380. + // Force frequency to 30MHz
  4381. + TOUCH_FREQ_OVERRIDE_30MHZ,
  4382. +
  4383. + // Force frequency to 50MHz (not currently supported)
  4384. + TOUCH_FREQ_OVERRIDE_50MHZ,
  4385. +
  4386. + // Invalid value
  4387. + TOUCH_FREQ_OVERRIDE_MAX
  4388. +};
  4389. +static_assert(sizeof(enum touch_freq_override) == 4);
  4390. +
  4391. +enum touch_spi_io_mode_override {
  4392. + // Do not apply any override
  4393. + TOUCH_SPI_IO_MODE_OVERRIDE_NONE,
  4394. +
  4395. + // Force Single I/O
  4396. + TOUCH_SPI_IO_MODE_OVERRIDE_SINGLE,
  4397. +
  4398. + // Force Dual I/O
  4399. + TOUCH_SPI_IO_MODE_OVERRIDE_DUAL,
  4400. +
  4401. + // Force Quad I/O
  4402. + TOUCH_SPI_IO_MODE_OVERRIDE_QUAD,
  4403. +
  4404. + // Invalid value
  4405. + TOUCH_SPI_IO_MODE_OVERRIDE_MAX
  4406. +};
  4407. +static_assert(sizeof(enum touch_spi_io_mode_override) == 4);
  4408. +
  4409. +struct touch_policy_data {
  4410. + // For future expansion.
  4411. + u32 reserved0;
  4412. +
  4413. + // Value in seconds, after which ME will put the sensor into Doze power
  4414. + // state if no activity occurs. Set to 0 to disable Doze mode
  4415. + // (not recommended). Value will be set to
  4416. + // TOUCH_DEFAULT_DOZE_TIMER_SECONDS by default
  4417. + u32 doze_timer:16;
  4418. +
  4419. + // Override frequency requested by sensor
  4420. + enum touch_freq_override freq_override:3;
  4421. +
  4422. + // Override IO mode requested by sensor
  4423. + enum touch_spi_io_mode_override spi_io_override :3;
  4424. +
  4425. + // For future expansion
  4426. + u32 reserved1:10;
  4427. +
  4428. + // For future expansion
  4429. + u32 reserved2;
  4430. +
  4431. + // Normally all bits will be zero. Bits will be defined as needed
  4432. + // for enabling special debug features
  4433. + u32 debug_override;
  4434. +};
  4435. +static_assert(sizeof(struct touch_policy_data) == 16);
  4436. +
  4437. +struct touch_sensor_set_policies_cmd_data {
  4438. + // Contains the desired policy to be set
  4439. + struct touch_policy_data policy_data;
  4440. +};
  4441. +static_assert(sizeof(struct touch_sensor_set_policies_cmd_data) == 16);
  4442. +
  4443. +enum touch_sensor_reset_type {
  4444. + // Hardware Reset using dedicated GPIO pin
  4445. + TOUCH_SENSOR_RESET_TYPE_HARD,
  4446. +
  4447. + // Software Reset using command written over SPI interface
  4448. + TOUCH_SENSOR_RESET_TYPE_SOFT,
  4449. +
  4450. + // Invalid value
  4451. + TOUCH_SENSOR_RESET_TYPE_MAX
  4452. +};
  4453. +static_assert(sizeof(enum touch_sensor_reset_type) == 4);
  4454. +
  4455. +struct touch_sensor_reset_cmd_data {
  4456. + // Indicate desired reset type
  4457. + enum touch_sensor_reset_type reset_type;
  4458. +
  4459. + // For future expansion
  4460. + u32 reserved;
  4461. +};
  4462. +static_assert(sizeof(struct touch_sensor_reset_cmd_data) == 8);
  4463. +
  4464. +/*
  4465. + * Host to ME message
  4466. + */
  4467. +union touch_sensor_data_h2m {
  4468. + struct touch_sensor_set_mode_cmd_data set_mode_cmd_data;
  4469. + struct touch_sensor_set_mem_window_cmd_data set_window_cmd_data;
  4470. + struct touch_sensor_quiesce_io_cmd_data quiesce_io_cmd_data;
  4471. + struct touch_sensor_feedback_ready_cmd_data feedback_ready_cmd_data;
  4472. + struct touch_sensor_set_policies_cmd_data set_policies_cmd_data;
  4473. + struct touch_sensor_reset_cmd_data reset_cmd_data;
  4474. +};
  4475. +struct touch_sensor_msg_h2m {
  4476. + u32 command_code;
  4477. + union touch_sensor_data_h2m h2m_data;
  4478. +};
  4479. +static_assert(sizeof(struct touch_sensor_msg_h2m) == 324);
  4480. +
  4481. +/*
  4482. + * Message structures used for ME to Host communication
  4483. + */
  4484. +
  4485. +// I/O mode values used by TOUCH_SENSOR_GET_DEVICE_INFO_RSP_DATA.
  4486. +enum touch_spi_io_mode {
  4487. + // Sensor set for Single I/O SPI
  4488. + TOUCH_SPI_IO_MODE_SINGLE = 0,
  4489. +
  4490. + // Sensor set for Dual I/O SPI
  4491. + TOUCH_SPI_IO_MODE_DUAL,
  4492. +
  4493. + // Sensor set for Quad I/O SPI
  4494. + TOUCH_SPI_IO_MODE_QUAD,
  4495. +
  4496. + // Invalid value
  4497. + TOUCH_SPI_IO_MODE_MAX
  4498. +};
  4499. +static_assert(sizeof(enum touch_spi_io_mode) == 4);
  4500. +
  4501. +/*
  4502. + * TOUCH_SENSOR_GET_DEVICE_INFO_RSP code is sent in response to
  4503. + * TOUCH_SENSOR_GET_DEVICE_INFO_CMD. This code will be followed by
  4504. + * TOUCH_SENSOR_GET_DEVICE_INFO_RSP_DATA.
  4505. + *
  4506. + * Possible Status values:
  4507. + * TOUCH_STATUS_SUCCESS:
  4508. + * Command was processed successfully and sensor
  4509. + * details are reported.
  4510. + *
  4511. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4512. + * Command sent did not match expected size. Other fields will
  4513. + * not contain valid data.
  4514. + *
  4515. + * TOUCH_STATUS_NO_SENSOR_FOUND:
  4516. + * Sensor has not yet been detected. Other fields will
  4517. + * not contain valid data.
  4518. + *
  4519. + * TOUCH_STATUS_INVALID_DEVICE_CAPS:
  4520. + * Indicates sensor does not support minimum required Frequency
  4521. + * or I/O Mode. ME firmware will choose best possible option for
  4522. + * the errant field. Caller should attempt to continue.
  4523. + *
  4524. + * TOUCH_STATUS_COMPAT_CHECK_FAIL:
  4525. + * Indicates TouchIC/ME compatibility mismatch. Caller should
  4526. + * attempt to continue.
  4527. + */
  4528. +struct touch_sensor_get_device_info_rsp_data {
  4529. + // Touch Sensor vendor ID
  4530. + u16 vendor_id;
  4531. +
  4532. + // Touch Sensor device ID
  4533. + u16 device_id;
  4534. +
  4535. + // Touch Sensor Hardware Revision
  4536. + u32 hw_rev;
  4537. +
  4538. + // Touch Sensor Firmware Revision
  4539. + u32 fw_rev;
  4540. +
  4541. + // Max size of one frame returned by Touch IC in bytes. This data
  4542. + // will be TOUCH_RAW_DATA_HDR followed by a payload. The payload can be
  4543. + // raw data or a HID structure depending on mode.
  4544. + u32 frame_size;
  4545. +
  4546. + // Max size of one Feedback structure in bytes
  4547. + u32 feedback_size;
  4548. +
  4549. + // Current operating mode of the sensor
  4550. + enum touch_sensor_mode sensor_mode;
  4551. +
  4552. + // Maximum number of simultaneous touch points that
  4553. + // can be reported by sensor
  4554. + u32 max_touch_points:8;
  4555. +
  4556. + // SPI bus Frequency supported by sensor and ME firmware
  4557. + enum touch_freq spi_frequency:8;
  4558. +
  4559. + // SPI bus I/O Mode supported by sensor and ME firmware
  4560. + enum touch_spi_io_mode spi_io_mode:8;
  4561. +
  4562. + // For future expansion
  4563. + u32 reserved0:8;
  4564. +
  4565. + // Minor version number of EDS spec supported by
  4566. + // sensor (from Compat Rev ID Reg)
  4567. + u8 sensor_minor_eds_rev;
  4568. +
  4569. + // Major version number of EDS spec supported by
  4570. + // sensor (from Compat Rev ID Reg)
  4571. + u8 sensor_major_eds_rev;
  4572. +
  4573. + // Minor version number of EDS spec supported by ME
  4574. + u8 me_minor_eds_rev;
  4575. +
  4576. + // Major version number of EDS spec supported by ME
  4577. + u8 me_major_eds_rev;
  4578. +
  4579. + // EDS Interface Revision Number supported by
  4580. + // sensor (from Compat Rev ID Reg)
  4581. + u8 sensor_eds_intf_rev;
  4582. +
  4583. + // EDS Interface Revision Number supported by ME
  4584. + u8 me_eds_intf_rev;
  4585. +
  4586. + // EU Kernel Compatibility Version (from Compat Rev ID Reg)
  4587. + u8 kernel_compat_ver;
  4588. +
  4589. + // For future expansion
  4590. + u8 reserved1;
  4591. +
  4592. + // For future expansion
  4593. + u32 reserved2[2];
  4594. +};
  4595. +static_assert(sizeof(struct touch_sensor_get_device_info_rsp_data) == 44);
  4596. +
  4597. +/*
  4598. + * TOUCH_SENSOR_SET_MODE_RSP code is sent in response to
  4599. + * TOUCH_SENSOR_SET_MODE_CMD. This code will be followed by
  4600. + * TOUCH_SENSOR_SET_MODE_RSP_DATA.
  4601. + *
  4602. + * Possible Status values:
  4603. + * TOUCH_STATUS_SUCCESS:
  4604. + * Command was processed successfully and mode was set.
  4605. + *
  4606. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4607. + * Command sent did not match expected size. Other fields will
  4608. + * not contain valid data.
  4609. + *
  4610. + * TOUCH_STATUS_INVALID_PARAMS:
  4611. + * Input parameters are out of range.
  4612. + */
  4613. +struct touch_sensor_set_mode_rsp_data {
  4614. + // For future expansion
  4615. + u32 reserved[3];
  4616. +};
  4617. +static_assert(sizeof(struct touch_sensor_set_mode_rsp_data) == 12);
  4618. +
  4619. +/*
  4620. + * TOUCH_SENSOR_SET_MEM_WINDOW_RSP code is sent in response to
  4621. + * TOUCH_SENSOR_SET_MEM_WINDOW_CMD. This code will be followed
  4622. + * by TOUCH_SENSOR_SET_MEM_WINDOW_RSP_DATA.
  4623. + *
  4624. + * Possible Status values:
  4625. + * TOUCH_STATUS_SUCCESS:
  4626. + * Command was processed successfully and memory window was set.
  4627. + *
  4628. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4629. + * Command sent did not match expected size. Other fields will
  4630. + * not contain valid data.
  4631. + *
  4632. + * TOUCH_STATUS_INVALID_PARAMS:
  4633. + * Input parameters are out of range.
  4634. + *
  4635. + * TOUCH_STATUS_ACCESS_DENIED:
  4636. + * Unable to map host address ranges for DMA.
  4637. + *
  4638. + * TOUCH_STATUS_OUT_OF_MEMORY:
  4639. + * Unable to allocate enough space for needed buffers.
  4640. + */
  4641. +struct touch_sensor_set_mem_window_rsp_data {
  4642. + // For future expansion
  4643. + u32 reserved[3];
  4644. +};
  4645. +static_assert(sizeof(struct touch_sensor_set_mem_window_rsp_data) == 12);
  4646. +
  4647. +/*
  4648. + * TOUCH_SENSOR_QUIESCE_IO_RSP code is sent in response to
  4649. + * TOUCH_SENSOR_QUIESCE_IO_CMD. This code will be followed
  4650. + * by TOUCH_SENSOR_QUIESCE_IO_RSP_DATA.
  4651. + *
  4652. + * Possible Status values:
  4653. + * TOUCH_STATUS_SUCCESS:
  4654. + * Command was processed successfully and touch flow has stopped.
  4655. + *
  4656. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4657. + * Command sent did not match expected size. Other fields will
  4658. + * not contain valid data.
  4659. + *
  4660. + * TOUCH_STATUS_QUIESCE_IO_IN_PROGRESS:
  4661. + * Indicates that Quiesce I/O is already in progress and this
  4662. + * command cannot be accepted at this time.
  4663. + *
  4664. + * TOUCH_STATIS_TIMEOUT:
  4665. + * Indicates ME timed out waiting for Quiesce I/O flow to complete.
  4666. + */
  4667. +struct touch_sensor_quiesce_io_rsp_data {
  4668. + // For future expansion
  4669. + u32 reserved[3];
  4670. +};
  4671. +static_assert(sizeof(struct touch_sensor_quiesce_io_rsp_data) == 12);
  4672. +
  4673. +// Reset Reason values used in TOUCH_SENSOR_HID_READY_FOR_DATA_RSP_DATA
  4674. +enum touch_reset_reason {
  4675. + // Reason for sensor reset is not known
  4676. + TOUCH_RESET_REASON_UNKNOWN = 0,
  4677. +
  4678. + // Reset was requested as part of TOUCH_SENSOR_FEEDBACK_READY_CMD
  4679. + TOUCH_RESET_REASON_FEEDBACK_REQUEST,
  4680. +
  4681. + // Reset was requested via TOUCH_SENSOR_RESET_CMD
  4682. + TOUCH_RESET_REASON_HECI_REQUEST,
  4683. +
  4684. + TOUCH_RESET_REASON_MAX
  4685. +};
  4686. +static_assert(sizeof(enum touch_reset_reason) == 4);
  4687. +
  4688. +/*
  4689. + * TOUCH_SENSOR_HID_READY_FOR_DATA_RSP code is sent in response to
  4690. + * TOUCH_SENSOR_HID_READY_FOR_DATA_CMD. This code will be followed
  4691. + * by TOUCH_SENSOR_HID_READY_FOR_DATA_RSP_DATA.
  4692. + *
  4693. + * Possible Status values:
  4694. + * TOUCH_STATUS_SUCCESS:
  4695. + * Command was processed successfully and HID data was sent by DMA.
  4696. + * This will only be sent in HID mode.
  4697. + *
  4698. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4699. + * Command sent did not match expected size. Other fields will
  4700. + * not contain valid data.
  4701. + *
  4702. + * TOUCH_STATUS_REQUEST_OUTSTANDING:
  4703. + * Previous request is still outstanding, ME FW cannot handle
  4704. + * another request for the same command.
  4705. + *
  4706. + * TOUCH_STATUS_NOT_READY:
  4707. + * Indicates memory window has not yet been set by BIOS/HID.
  4708. + *
  4709. + * TOUCH_STATUS_SENSOR_DISABLED:
  4710. + * Indicates that ME to HID communication has been stopped either
  4711. + * by TOUCH_SENSOR_QUIESCE_IO_CMD or
  4712. + * TOUCH_SENSOR_CLEAR_MEM_WINDOW_CMD.
  4713. + *
  4714. + * TOUCH_STATUS_SENSOR_UNEXPECTED_RESET:
  4715. + * Sensor signaled a Reset Interrupt. ME did not expect this and
  4716. + * has no info about why this occurred.
  4717. + *
  4718. + * TOUCH_STATUS_SENSOR_EXPECTED_RESET:
  4719. + * Sensor signaled a Reset Interrupt. ME either directly requested
  4720. + * this reset, or it was expected as part of a defined flow
  4721. + * in the EDS.
  4722. + *
  4723. + * TOUCH_STATUS_QUIESCE_IO_IN_PROGRESS:
  4724. + * Indicates that Quiesce I/O is already in progress and this
  4725. + * command cannot be accepted at this time.
  4726. + *
  4727. + * TOUCH_STATUS_TIMEOUT:
  4728. + * Sensor did not generate a reset interrupt in the time allotted.
  4729. + * Could indicate sensor is not connected or malfunctioning.
  4730. + */
  4731. +struct touch_sensor_hid_ready_for_data_rsp_data {
  4732. + // Size of the data the ME DMA'd into a RawDataBuffer.
  4733. + // Valid only when Status == TOUCH_STATUS_SUCCESS
  4734. + u32 data_size;
  4735. +
  4736. + // Index to indicate which RawDataBuffer was used.
  4737. + // Valid only when Status == TOUCH_STATUS_SUCCESS
  4738. + u8 touch_data_buffer_index;
  4739. +
  4740. + // If Status is TOUCH_STATUS_SENSOR_EXPECTED_RESET, ME will provide
  4741. + // the cause. See TOUCH_RESET_REASON.
  4742. + u8 reset_reason;
  4743. +
  4744. + // For future expansion
  4745. + u8 reserved1[2];
  4746. + u32 reserved2[5];
  4747. +};
  4748. +static_assert(sizeof(struct touch_sensor_hid_ready_for_data_rsp_data) == 28);
  4749. +
  4750. +/*
  4751. + * TOUCH_SENSOR_FEEDBACK_READY_RSP code is sent in response to
  4752. + * TOUCH_SENSOR_FEEDBACK_READY_CMD. This code will be followed
  4753. + * by TOUCH_SENSOR_FEEDBACK_READY_RSP_DATA.
  4754. + *
  4755. + * Possible Status values:
  4756. + * TOUCH_STATUS_SUCCESS:
  4757. + * Command was processed successfully and any feedback or
  4758. + * commands were sent to sensor.
  4759. + *
  4760. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4761. + * Command sent did not match expected size. Other fields will
  4762. + * not contain valid data.
  4763. + *
  4764. + * TOUCH_STATUS_INVALID_PARAMS:
  4765. + * Input parameters are out of range.
  4766. + *
  4767. + * TOUCH_STATUS_COMPAT_CHECK_FAIL:
  4768. + * Indicates ProtocolVer does not match ME supported
  4769. + * version. (non-fatal error)
  4770. + *
  4771. + * TOUCH_STATUS_INTERNAL_ERROR:
  4772. + * Unexpected error occurred. This should not normally be seen.
  4773. + *
  4774. + * TOUCH_STATUS_OUT_OF_MEMORY:
  4775. + * Insufficient space to store Calibration Data
  4776. + */
  4777. +struct touch_sensor_feedback_ready_rsp_data {
  4778. + // Index value from 0 to TOUCH_SENSOR_MAX_DATA_BUFFERS used
  4779. + // to indicate which Feedback Buffer to use
  4780. + u8 feedback_index;
  4781. +
  4782. + // For future expansion
  4783. + u8 reserved1[3];
  4784. + u32 reserved2[6];
  4785. +};
  4786. +static_assert(sizeof(struct touch_sensor_feedback_ready_rsp_data) == 28);
  4787. +
  4788. +/*
  4789. + * TOUCH_SENSOR_CLEAR_MEM_WINDOW_RSP code is sent in response to
  4790. + * TOUCH_SENSOR_CLEAR_MEM_WINDOW_CMD. This code will be followed
  4791. + * by TOUCH_SENSOR_CLEAR_MEM_WINDOW_RSP_DATA.
  4792. + *
  4793. + * Possible Status values:
  4794. + * TOUCH_STATUS_SUCCESS:
  4795. + * Command was processed successfully and memory window was set.
  4796. + *
  4797. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4798. + * Command sent did not match expected size. Other fields will
  4799. + * not contain valid data.
  4800. + *
  4801. + * TOUCH_STATUS_INVALID_PARAMS:
  4802. + * Input parameters are out of range.
  4803. + *
  4804. + * TOUCH_STATUS_QUIESCE_IO_IN_PROGRESS:
  4805. + * Indicates that Quiesce I/O is already in progress and this
  4806. + * command cannot be accepted at this time.
  4807. + */
  4808. +struct touch_sensor_clear_mem_window_rsp_data {
  4809. + // For future expansion
  4810. + u32 reserved[3];
  4811. +};
  4812. +static_assert(sizeof(struct touch_sensor_clear_mem_window_rsp_data) == 12);
  4813. +
  4814. +/*
  4815. + * TOUCH_SENSOR_NOTIFY_DEV_READY_RSP code is sent in response to
  4816. + * TOUCH_SENSOR_NOTIFY_DEV_READY_CMD. This code will be followed
  4817. + * by TOUCH_SENSOR_NOTIFY_DEV_READY_RSP_DATA.
  4818. + *
  4819. + * Possible Status values:
  4820. + * TOUCH_STATUS_SUCCESS:
  4821. + * Command was processed successfully and sensor has
  4822. + * been detected by ME FW.
  4823. + *
  4824. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4825. + * Command sent did not match expected size.
  4826. + *
  4827. + * TOUCH_STATUS_REQUEST_OUTSTANDING:
  4828. + * Previous request is still outstanding, ME FW cannot handle
  4829. + * another request for the same command.
  4830. + *
  4831. + * TOUCH_STATUS_TIMEOUT:
  4832. + * Sensor did not generate a reset interrupt in the time allotted.
  4833. + * Could indicate sensor is not connected or malfunctioning.
  4834. + *
  4835. + * TOUCH_STATUS_SENSOR_FAIL_FATAL:
  4836. + * Sensor indicated a fatal error, further operation is not
  4837. + * possible. Error details can be found in ErrReg.
  4838. + *
  4839. + * TOUCH_STATUS_SENSOR_FAIL_NONFATAL:
  4840. + * Sensor indicated a non-fatal error. Error should be logged by
  4841. + * caller and init flow can continue. Error details can be found
  4842. + * in ErrReg.
  4843. + */
  4844. +struct touch_sensor_notify_dev_ready_rsp_data {
  4845. + // Value of sensor Error Register, field is only valid for
  4846. + // Status == TOUCH_STATUS_SENSOR_FAIL_FATAL or
  4847. + // TOUCH_STATUS_SENSOR_FAIL_NONFATAL
  4848. + union touch_err_reg err_reg;
  4849. +
  4850. + // For future expansion
  4851. + u32 reserved[2];
  4852. +};
  4853. +static_assert(sizeof(struct touch_sensor_notify_dev_ready_rsp_data) == 12);
  4854. +
  4855. +/*
  4856. + * TOUCH_SENSOR_SET_POLICIES_RSP code is sent in response to
  4857. + * TOUCH_SENSOR_SET_POLICIES_CMD. This code will be followed
  4858. + * by TOUCH_SENSOR_SET_POLICIES_RSP_DATA.
  4859. + *
  4860. + * Possible Status values:
  4861. + * TOUCH_STATUS_SUCCESS:
  4862. + * Command was processed successfully and new policies were set.
  4863. + *
  4864. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4865. + * Command sent did not match expected size. Other fields will
  4866. + * not contain valid data.
  4867. + *
  4868. + * TOUCH_STATUS_INVALID_PARAMS:
  4869. + * Input parameters are out of range.
  4870. + */
  4871. +struct touch_sensor_set_policies_rsp_data {
  4872. + // For future expansion
  4873. + u32 reserved[3];
  4874. +};
  4875. +static_assert(sizeof(struct touch_sensor_set_policies_rsp_data) == 12);
  4876. +
  4877. +/*
  4878. + * TOUCH_SENSOR_GET_POLICIES_RSP code is sent in response to
  4879. + * TOUCH_SENSOR_GET_POLICIES_CMD. This code will be followed
  4880. + * by TOUCH_SENSOR_GET_POLICIES_RSP_DATA.
  4881. + *
  4882. + * Possible Status values:
  4883. + * TOUCH_STATUS_SUCCESS:
  4884. + * Command was processed successfully and new policies were set.
  4885. + *
  4886. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4887. + * Command sent did not match expected size. Other fields will
  4888. + * not contain valid data.
  4889. + */
  4890. +struct touch_sensor_get_policies_rsp_data {
  4891. + // Contains the current policy
  4892. + struct touch_policy_data policy_data;
  4893. +};
  4894. +static_assert(sizeof(struct touch_sensor_get_policies_rsp_data) == 16);
  4895. +
  4896. +
  4897. +/*
  4898. + * TOUCH_SENSOR_RESET_RSP code is sent in response to
  4899. + * TOUCH_SENSOR_RESET_CMD. This code will be followed
  4900. + * by TOUCH_SENSOR_RESET_RSP_DATA.
  4901. + *
  4902. + * Possible Status values:
  4903. + * TOUCH_STATUS_SUCCESS:
  4904. + * Command was processed successfully and
  4905. + * sensor reset was completed.
  4906. + *
  4907. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4908. + * Command sent did not match expected size. Other fields will
  4909. + * not contain valid data.
  4910. + *
  4911. + * TOUCH_STATUS_INVALID_PARAMS:
  4912. + * Input parameters are out of range.
  4913. + *
  4914. + * TOUCH_STATUS_TIMEOUT:
  4915. + * Sensor did not generate a reset interrupt in the time allotted.
  4916. + * Could indicate sensor is not connected or malfunctioning.
  4917. + *
  4918. + * TOUCH_STATUS_RESET_FAILED:
  4919. + * Sensor generated an invalid or unexpected interrupt.
  4920. + *
  4921. + * TOUCH_STATUS_QUIESCE_IO_IN_PROGRESS:
  4922. + * Indicates that Quiesce I/O is already in progress and this
  4923. + * command cannot be accepted at this time.
  4924. + */
  4925. +struct touch_sensor_reset_rsp_data {
  4926. + // For future expansion
  4927. + u32 reserved[3];
  4928. +};
  4929. +static_assert(sizeof(struct touch_sensor_reset_rsp_data) == 12);
  4930. +
  4931. +/*
  4932. + * TOUCH_SENSOR_READ_ALL_REGS_RSP code is sent in response to
  4933. + * TOUCH_SENSOR_READ_ALL_REGS_CMD. This code will be followed
  4934. + * by TOUCH_SENSOR_READ_ALL_REGS_RSP_DATA.
  4935. + *
  4936. + * Possible Status values:
  4937. + * TOUCH_STATUS_SUCCESS:
  4938. + * Command was processed successfully and new policies were set.
  4939. + * TOUCH_STATUS_CMD_SIZE_ERROR:
  4940. + * Command sent did not match expected size. Other fields will
  4941. + * not contain valid data.
  4942. + */
  4943. +struct touch_sensor_read_all_regs_rsp_data {
  4944. + // Returns first 64 bytes of register space used for normal
  4945. + // touch operation. Does not include test mode register.
  4946. + struct touch_reg_block sensor_regs;
  4947. + u32 reserved[4];
  4948. +};
  4949. +static_assert(sizeof(struct touch_sensor_read_all_regs_rsp_data) == 80);
  4950. +
  4951. +/*
  4952. + * ME to Host Message
  4953. + */
  4954. +union touch_sensor_data_m2h {
  4955. + struct touch_sensor_get_device_info_rsp_data device_info_rsp_data;
  4956. + struct touch_sensor_set_mode_rsp_data set_mode_rsp_data;
  4957. + struct touch_sensor_set_mem_window_rsp_data set_mem_window_rsp_data;
  4958. + struct touch_sensor_quiesce_io_rsp_data quiesce_io_rsp_data;
  4959. +
  4960. + struct touch_sensor_hid_ready_for_data_rsp_data
  4961. + hid_ready_for_data_rsp_data;
  4962. +
  4963. + struct touch_sensor_feedback_ready_rsp_data feedback_ready_rsp_data;
  4964. + struct touch_sensor_clear_mem_window_rsp_data clear_mem_window_rsp_data;
  4965. + struct touch_sensor_notify_dev_ready_rsp_data notify_dev_ready_rsp_data;
  4966. + struct touch_sensor_set_policies_rsp_data set_policies_rsp_data;
  4967. + struct touch_sensor_get_policies_rsp_data get_policies_rsp_data;
  4968. + struct touch_sensor_reset_rsp_data reset_rsp_data;
  4969. + struct touch_sensor_read_all_regs_rsp_data read_all_regs_rsp_data;
  4970. +};
  4971. +struct touch_sensor_msg_m2h {
  4972. + u32 command_code;
  4973. + enum touch_status status;
  4974. + union touch_sensor_data_m2h m2h_data;
  4975. +};
  4976. +static_assert(sizeof(struct touch_sensor_msg_m2h) == 88);
  4977. +
  4978. +#pragma pack()
  4979. +
  4980. +#endif // _IPTS_MEI_MSGS_H_
  4981. diff --git a/drivers/misc/ipts/mei.c b/drivers/misc/ipts/mei.c
  4982. new file mode 100644
  4983. index 0000000000000..03b5d747a728f
  4984. --- /dev/null
  4985. +++ b/drivers/misc/ipts/mei.c
  4986. @@ -0,0 +1,238 @@
  4987. +// SPDX-License-Identifier: GPL-2.0-or-later
  4988. +/*
  4989. + *
  4990. + * Intel Precise Touch & Stylus
  4991. + * Copyright (c) 2016 Intel Corporation
  4992. + *
  4993. + */
  4994. +
  4995. +#include <linux/dma-mapping.h>
  4996. +#include <linux/hid.h>
  4997. +#include <linux/ipts-binary.h>
  4998. +#include <linux/kthread.h>
  4999. +#include <linux/mei_cl_bus.h>
  5000. +#include <linux/module.h>
  5001. +#include <linux/mod_devicetable.h>
  5002. +
  5003. +#include "companion.h"
  5004. +#include "hid.h"
  5005. +#include "ipts.h"
  5006. +#include "params.h"
  5007. +#include "msg-handler.h"
  5008. +#include "mei-msgs.h"
  5009. +#include "state.h"
  5010. +
  5011. +#define IPTS_DRIVER_NAME "ipts"
  5012. +#define IPTS_MEI_UUID UUID_LE(0x3e8d0870, 0x271a, 0x4208, \
  5013. + 0x8e, 0xb5, 0x9a, 0xcb, 0x94, 0x02, 0xae, 0x04)
  5014. +
  5015. +static struct mei_cl_device_id ipts_mei_cl_tbl[] = {
  5016. + { "", IPTS_MEI_UUID, MEI_CL_VERSION_ANY },
  5017. + { }
  5018. +};
  5019. +MODULE_DEVICE_TABLE(mei, ipts_mei_cl_tbl);
  5020. +
  5021. +static ssize_t device_info_show(struct device *dev,
  5022. + struct device_attribute *attr, char *buf)
  5023. +{
  5024. + struct ipts_info *ipts;
  5025. +
  5026. + ipts = dev_get_drvdata(dev);
  5027. + return sprintf(buf, "vendor id = 0x%04hX\ndevice id = 0x%04hX\n"
  5028. + "HW rev = 0x%08X\nfirmware rev = 0x%08X\n",
  5029. + ipts->device_info.vendor_id, ipts->device_info.device_id,
  5030. + ipts->device_info.hw_rev, ipts->device_info.fw_rev);
  5031. +}
  5032. +static DEVICE_ATTR_RO(device_info);
  5033. +
  5034. +static struct attribute *ipts_attrs[] = {
  5035. + &dev_attr_device_info.attr,
  5036. + NULL
  5037. +};
  5038. +
  5039. +static const struct attribute_group ipts_grp = {
  5040. + .attrs = ipts_attrs,
  5041. +};
  5042. +
  5043. +static void raw_data_work_func(struct work_struct *work)
  5044. +{
  5045. + struct ipts_info *ipts = container_of(work,
  5046. + struct ipts_info, raw_data_work);
  5047. +
  5048. + ipts_handle_processed_data(ipts);
  5049. +}
  5050. +
  5051. +static void gfx_status_work_func(struct work_struct *work)
  5052. +{
  5053. + struct ipts_info *ipts = container_of(work, struct ipts_info,
  5054. + gfx_status_work);
  5055. + enum ipts_state state;
  5056. + int status = ipts->gfx_status;
  5057. +
  5058. + ipts_dbg(ipts, "notify gfx status : %d\n", status);
  5059. +
  5060. + state = ipts_get_state(ipts);
  5061. +
  5062. + if (state != IPTS_STA_RAW_DATA_STARTED && state != IPTS_STA_HID_STARTED)
  5063. + return;
  5064. +
  5065. + if (status == IPTS_NOTIFY_STA_BACKLIGHT_ON && !ipts->display_status) {
  5066. + ipts_send_sensor_clear_mem_window_cmd(ipts);
  5067. + ipts->display_status = true;
  5068. + }
  5069. +
  5070. + if (status == IPTS_NOTIFY_STA_BACKLIGHT_OFF && ipts->display_status) {
  5071. + ipts_send_sensor_quiesce_io_cmd(ipts);
  5072. + ipts->display_status = false;
  5073. + }
  5074. +}
  5075. +
  5076. +// event loop
  5077. +static int ipts_mei_cl_event_thread(void *data)
  5078. +{
  5079. + struct ipts_info *ipts = (struct ipts_info *)data;
  5080. + struct mei_cl_device *cldev = ipts->cldev;
  5081. + ssize_t msg_len;
  5082. + struct touch_sensor_msg_m2h m2h_msg;
  5083. +
  5084. + while (!kthread_should_stop()) {
  5085. + msg_len = mei_cldev_recv(cldev,
  5086. + (u8 *)&m2h_msg, sizeof(m2h_msg));
  5087. + if (msg_len <= 0) {
  5088. + ipts_err(ipts, "error in reading m2h msg\n");
  5089. + continue;
  5090. + }
  5091. +
  5092. + if (ipts_handle_resp(ipts, &m2h_msg, msg_len) != 0)
  5093. + ipts_err(ipts, "error in handling resp msg\n");
  5094. + }
  5095. +
  5096. + ipts_dbg(ipts, "!! end event loop !!\n");
  5097. +
  5098. + return 0;
  5099. +}
  5100. +
  5101. +static void init_work_func(struct work_struct *work)
  5102. +{
  5103. + struct ipts_info *ipts = container_of(work,
  5104. + struct ipts_info, init_work);
  5105. +
  5106. + ipts->sensor_mode = TOUCH_SENSOR_MODE_RAW_DATA;
  5107. + ipts->display_status = true;
  5108. +
  5109. + ipts_start(ipts);
  5110. +}
  5111. +
  5112. +static int ipts_mei_cl_probe(struct mei_cl_device *cldev,
  5113. + const struct mei_cl_device_id *id)
  5114. +{
  5115. + int ret = 0;
  5116. + struct ipts_info *ipts = NULL;
  5117. +
  5118. + // Check if a companion driver for firmware loading was registered
  5119. + // If not, defer probing until it was properly registered
  5120. + if (!ipts_companion_available() && !ipts_modparams.ignore_companion)
  5121. + return -EPROBE_DEFER;
  5122. +
  5123. + pr_info("probing Intel Precise Touch & Stylus\n");
  5124. +
  5125. + // setup the DMA BIT mask, the system will choose the best possible
  5126. + if (dma_coerce_mask_and_coherent(&cldev->dev, DMA_BIT_MASK(64)) == 0) {
  5127. + pr_info("IPTS using DMA_BIT_MASK(64)\n");
  5128. + } else if (dma_coerce_mask_and_coherent(&cldev->dev,
  5129. + DMA_BIT_MASK(32)) == 0) {
  5130. + pr_info("IPTS using DMA_BIT_MASK(32)\n");
  5131. + } else {
  5132. + pr_err("IPTS: No suitable DMA available\n");
  5133. + return -EFAULT;
  5134. + }
  5135. +
  5136. + ret = mei_cldev_enable(cldev);
  5137. + if (ret < 0) {
  5138. + pr_err("cannot enable IPTS\n");
  5139. + return ret;
  5140. + }
  5141. +
  5142. + ipts = devm_kzalloc(&cldev->dev, sizeof(struct ipts_info), GFP_KERNEL);
  5143. + if (ipts == NULL) {
  5144. + ret = -ENOMEM;
  5145. + goto disable_mei;
  5146. + }
  5147. +
  5148. + ipts->cldev = cldev;
  5149. + mei_cldev_set_drvdata(cldev, ipts);
  5150. + ipts->event_loop = kthread_run(ipts_mei_cl_event_thread, (void *)ipts,
  5151. + "ipts_event_thread");
  5152. +
  5153. + if (ipts_dbgfs_register(ipts, "ipts"))
  5154. + pr_debug("cannot register debugfs for IPTS\n");
  5155. +
  5156. + INIT_WORK(&ipts->init_work, init_work_func);
  5157. + INIT_WORK(&ipts->raw_data_work, raw_data_work_func);
  5158. + INIT_WORK(&ipts->gfx_status_work, gfx_status_work_func);
  5159. +
  5160. + ret = sysfs_create_group(&cldev->dev.kobj, &ipts_grp);
  5161. + if (ret != 0)
  5162. + pr_debug("cannot create sysfs for IPTS\n");
  5163. +
  5164. + schedule_work(&ipts->init_work);
  5165. +
  5166. + return 0;
  5167. +
  5168. +disable_mei:
  5169. + mei_cldev_disable(cldev);
  5170. +
  5171. + return ret;
  5172. +}
  5173. +
  5174. +static int ipts_mei_cl_remove(struct mei_cl_device *cldev)
  5175. +{
  5176. + struct ipts_info *ipts = mei_cldev_get_drvdata(cldev);
  5177. +
  5178. + ipts_stop(ipts);
  5179. +
  5180. + sysfs_remove_group(&cldev->dev.kobj, &ipts_grp);
  5181. + ipts_hid_release(ipts);
  5182. + ipts_dbgfs_deregister(ipts);
  5183. + mei_cldev_disable(cldev);
  5184. +
  5185. + kthread_stop(ipts->event_loop);
  5186. +
  5187. + pr_info("IPTS removed\n");
  5188. +
  5189. + return 0;
  5190. +}
  5191. +
  5192. +static struct mei_cl_driver ipts_mei_cl_driver = {
  5193. + .id_table = ipts_mei_cl_tbl,
  5194. + .name = IPTS_DRIVER_NAME,
  5195. + .probe = ipts_mei_cl_probe,
  5196. + .remove = ipts_mei_cl_remove,
  5197. +};
  5198. +
  5199. +static int ipts_mei_cl_init(void)
  5200. +{
  5201. + int ret;
  5202. +
  5203. + pr_info("IPTS %s() is called\n", __func__);
  5204. +
  5205. + ret = mei_cldev_driver_register(&ipts_mei_cl_driver);
  5206. + if (ret) {
  5207. + pr_err("unable to register IPTS mei client driver\n");
  5208. + return ret;
  5209. + }
  5210. +
  5211. + return 0;
  5212. +}
  5213. +
  5214. +static void __exit ipts_mei_cl_exit(void)
  5215. +{
  5216. + pr_info("IPTS %s() is called\n", __func__);
  5217. + mei_cldev_driver_unregister(&ipts_mei_cl_driver);
  5218. +}
  5219. +
  5220. +module_init(ipts_mei_cl_init);
  5221. +module_exit(ipts_mei_cl_exit);
  5222. +
  5223. +MODULE_DESCRIPTION("Intel(R) ME Interface Client Driver for IPTS");
  5224. +MODULE_LICENSE("GPL");
  5225. diff --git a/drivers/misc/ipts/msg-handler.c b/drivers/misc/ipts/msg-handler.c
  5226. new file mode 100644
  5227. index 0000000000000..9431b1dfc6e06
  5228. --- /dev/null
  5229. +++ b/drivers/misc/ipts/msg-handler.c
  5230. @@ -0,0 +1,405 @@
  5231. +// SPDX-License-Identifier: GPL-2.0-or-later
  5232. +/*
  5233. + *
  5234. + * Intel Precise Touch & Stylus
  5235. + * Copyright (c) 2016 Intel Corporation
  5236. + *
  5237. + */
  5238. +
  5239. +#include <linux/mei_cl_bus.h>
  5240. +
  5241. +#include "hid.h"
  5242. +#include "ipts.h"
  5243. +#include "mei-msgs.h"
  5244. +#include "resource.h"
  5245. +
  5246. +#define rsp_failed(ipts, cmd, status) \
  5247. + ipts_err(ipts, "0x%08x failed status = %d\n", cmd, status)
  5248. +
  5249. +int ipts_handle_cmd(struct ipts_info *ipts, u32 cmd, void *data, int data_size)
  5250. +{
  5251. + int ret = 0;
  5252. + int len = 0;
  5253. + struct touch_sensor_msg_h2m h2m_msg;
  5254. +
  5255. + memset(&h2m_msg, 0, sizeof(h2m_msg));
  5256. +
  5257. + h2m_msg.command_code = cmd;
  5258. + len = sizeof(h2m_msg.command_code) + data_size;
  5259. +
  5260. + if (data != NULL && data_size != 0)
  5261. + memcpy(&h2m_msg.h2m_data, data, data_size); // copy payload
  5262. +
  5263. + ret = mei_cldev_send(ipts->cldev, (u8 *)&h2m_msg, len);
  5264. + if (ret < 0) {
  5265. + ipts_err(ipts, "mei_cldev_send() error 0x%X:%d\n", cmd, ret);
  5266. + return ret;
  5267. + }
  5268. +
  5269. + return 0;
  5270. +}
  5271. +
  5272. +int ipts_send_feedback(struct ipts_info *ipts, int buffer_idx,
  5273. + u32 transaction_id)
  5274. +{
  5275. + struct ipts_buffer_info feedback_buffer;
  5276. + struct touch_feedback_hdr *feedback;
  5277. + struct touch_sensor_feedback_ready_cmd_data cmd;
  5278. +
  5279. + feedback_buffer = ipts->resource.feedback_buffer[buffer_idx];
  5280. + feedback = (struct touch_feedback_hdr *)feedback_buffer.addr;
  5281. +
  5282. + memset(feedback, 0, sizeof(struct touch_feedback_hdr));
  5283. + memset(&cmd, 0, sizeof(struct touch_sensor_feedback_ready_cmd_data));
  5284. +
  5285. + feedback->feedback_cmd_type = TOUCH_FEEDBACK_CMD_TYPE_NONE;
  5286. + feedback->buffer_id = transaction_id;
  5287. +
  5288. + cmd.feedback_index = buffer_idx;
  5289. + cmd.transaction_id = transaction_id;
  5290. +
  5291. + return ipts_handle_cmd(ipts, TOUCH_SENSOR_FEEDBACK_READY_CMD,
  5292. + &cmd, sizeof(struct touch_sensor_feedback_ready_cmd_data));
  5293. +}
  5294. +
  5295. +int ipts_send_sensor_quiesce_io_cmd(struct ipts_info *ipts)
  5296. +{
  5297. + int cmd_len = sizeof(struct touch_sensor_quiesce_io_cmd_data);
  5298. + struct touch_sensor_quiesce_io_cmd_data quiesce_io_cmd;
  5299. +
  5300. + memset(&quiesce_io_cmd, 0, cmd_len);
  5301. +
  5302. + return ipts_handle_cmd(ipts, TOUCH_SENSOR_QUIESCE_IO_CMD,
  5303. + &quiesce_io_cmd, cmd_len);
  5304. +}
  5305. +
  5306. +int ipts_send_sensor_hid_ready_for_data_cmd(struct ipts_info *ipts)
  5307. +{
  5308. + return ipts_handle_cmd(ipts,
  5309. + TOUCH_SENSOR_HID_READY_FOR_DATA_CMD, NULL, 0);
  5310. +}
  5311. +
  5312. +int ipts_send_sensor_clear_mem_window_cmd(struct ipts_info *ipts)
  5313. +{
  5314. + return ipts_handle_cmd(ipts,
  5315. + TOUCH_SENSOR_CLEAR_MEM_WINDOW_CMD, NULL, 0);
  5316. +}
  5317. +
  5318. +static int check_validity(struct touch_sensor_msg_m2h *m2h_msg, u32 msg_len)
  5319. +{
  5320. + int ret = 0;
  5321. + int valid_msg_len = sizeof(m2h_msg->command_code);
  5322. + u32 cmd_code = m2h_msg->command_code;
  5323. +
  5324. + switch (cmd_code) {
  5325. + case TOUCH_SENSOR_SET_MODE_RSP:
  5326. + valid_msg_len +=
  5327. + sizeof(struct touch_sensor_set_mode_rsp_data);
  5328. + break;
  5329. + case TOUCH_SENSOR_SET_MEM_WINDOW_RSP:
  5330. + valid_msg_len +=
  5331. + sizeof(struct touch_sensor_set_mem_window_rsp_data);
  5332. + break;
  5333. + case TOUCH_SENSOR_QUIESCE_IO_RSP:
  5334. + valid_msg_len +=
  5335. + sizeof(struct touch_sensor_quiesce_io_rsp_data);
  5336. + break;
  5337. + case TOUCH_SENSOR_HID_READY_FOR_DATA_RSP:
  5338. + valid_msg_len +=
  5339. + sizeof(struct touch_sensor_hid_ready_for_data_rsp_data);
  5340. + break;
  5341. + case TOUCH_SENSOR_FEEDBACK_READY_RSP:
  5342. + valid_msg_len +=
  5343. + sizeof(struct touch_sensor_feedback_ready_rsp_data);
  5344. + break;
  5345. + case TOUCH_SENSOR_CLEAR_MEM_WINDOW_RSP:
  5346. + valid_msg_len +=
  5347. + sizeof(struct touch_sensor_clear_mem_window_rsp_data);
  5348. + break;
  5349. + case TOUCH_SENSOR_NOTIFY_DEV_READY_RSP:
  5350. + valid_msg_len +=
  5351. + sizeof(struct touch_sensor_notify_dev_ready_rsp_data);
  5352. + break;
  5353. + case TOUCH_SENSOR_SET_POLICIES_RSP:
  5354. + valid_msg_len +=
  5355. + sizeof(struct touch_sensor_set_policies_rsp_data);
  5356. + break;
  5357. + case TOUCH_SENSOR_GET_POLICIES_RSP:
  5358. + valid_msg_len +=
  5359. + sizeof(struct touch_sensor_get_policies_rsp_data);
  5360. + break;
  5361. + case TOUCH_SENSOR_RESET_RSP:
  5362. + valid_msg_len +=
  5363. + sizeof(struct touch_sensor_reset_rsp_data);
  5364. + break;
  5365. + }
  5366. +
  5367. + if (valid_msg_len != msg_len)
  5368. + return -EINVAL;
  5369. + return ret;
  5370. +}
  5371. +
  5372. +int ipts_start(struct ipts_info *ipts)
  5373. +{
  5374. + /*
  5375. + * TODO: check if we need to do SET_POLICIES_CMD we need to do this
  5376. + * when protocol version doesn't match with reported one how we keep
  5377. + * vendor specific data is the first thing to solve.
  5378. + */
  5379. + ipts_set_state(ipts, IPTS_STA_INIT);
  5380. + ipts->num_of_parallel_data_buffers = TOUCH_SENSOR_MAX_DATA_BUFFERS;
  5381. +
  5382. + // start with RAW_DATA
  5383. + ipts->sensor_mode = TOUCH_SENSOR_MODE_RAW_DATA;
  5384. +
  5385. + return ipts_handle_cmd(ipts,
  5386. + TOUCH_SENSOR_NOTIFY_DEV_READY_CMD, NULL, 0);
  5387. +}
  5388. +
  5389. +void ipts_stop(struct ipts_info *ipts)
  5390. +{
  5391. + enum ipts_state old_state = ipts_get_state(ipts);
  5392. +
  5393. + ipts_set_state(ipts, IPTS_STA_STOPPING);
  5394. +
  5395. + ipts_send_sensor_quiesce_io_cmd(ipts);
  5396. + ipts_send_sensor_clear_mem_window_cmd(ipts);
  5397. +
  5398. + if (old_state < IPTS_STA_RESOURCE_READY)
  5399. + return;
  5400. +
  5401. + if (old_state == IPTS_STA_RAW_DATA_STARTED ||
  5402. + old_state == IPTS_STA_HID_STARTED) {
  5403. + ipts_free_default_resource(ipts);
  5404. + ipts_free_raw_data_resource(ipts);
  5405. + }
  5406. +}
  5407. +
  5408. +int ipts_restart(struct ipts_info *ipts)
  5409. +{
  5410. + ipts_dbg(ipts, "ipts restart\n");
  5411. + ipts_stop(ipts);
  5412. +
  5413. + ipts_send_sensor_quiesce_io_cmd(ipts);
  5414. + ipts->restart = true;
  5415. +
  5416. + return 0;
  5417. +}
  5418. +
  5419. +int ipts_handle_resp(struct ipts_info *ipts,
  5420. + struct touch_sensor_msg_m2h *m2h_msg, u32 msg_len)
  5421. +{
  5422. + int ret = 0;
  5423. + int rsp_status = 0;
  5424. + int cmd_status = 0;
  5425. + int cmd_len = 0;
  5426. + u32 cmd;
  5427. +
  5428. + if (!check_validity(m2h_msg, msg_len)) {
  5429. + ipts_err(ipts, "wrong rsp\n");
  5430. + return -EINVAL;
  5431. + }
  5432. +
  5433. + rsp_status = m2h_msg->status;
  5434. + cmd = m2h_msg->command_code;
  5435. +
  5436. + switch (cmd) {
  5437. + case TOUCH_SENSOR_NOTIFY_DEV_READY_RSP: {
  5438. + if (rsp_status != TOUCH_STATUS_SENSOR_FAIL_NONFATAL &&
  5439. + rsp_status != 0) {
  5440. + rsp_failed(ipts, cmd, rsp_status);
  5441. + break;
  5442. + }
  5443. +
  5444. + cmd_status = ipts_handle_cmd(ipts,
  5445. + TOUCH_SENSOR_GET_DEVICE_INFO_CMD, NULL, 0);
  5446. +
  5447. + break;
  5448. + }
  5449. + case TOUCH_SENSOR_GET_DEVICE_INFO_RSP: {
  5450. + if (rsp_status != TOUCH_STATUS_COMPAT_CHECK_FAIL &&
  5451. + rsp_status != 0) {
  5452. + rsp_failed(ipts, cmd, rsp_status);
  5453. + break;
  5454. + }
  5455. +
  5456. + memcpy(&ipts->device_info,
  5457. + &m2h_msg->m2h_data.device_info_rsp_data,
  5458. + sizeof(struct touch_sensor_get_device_info_rsp_data));
  5459. +
  5460. + /*
  5461. + * TODO: support raw_request during HID init. Although HID
  5462. + * init happens here, technically most of reports
  5463. + * (for both direction) can be issued only after
  5464. + * SET_MEM_WINDOWS_CMD since they may require ME or touch IC.
  5465. + * If ipts vendor requires raw_request during HID init, we
  5466. + * need to consider to move HID init.
  5467. + */
  5468. + if (ipts->hid_desc_ready == false) {
  5469. + ret = ipts_hid_init(ipts);
  5470. + if (ret)
  5471. + break;
  5472. + }
  5473. +
  5474. + cmd_status = ipts_send_sensor_clear_mem_window_cmd(ipts);
  5475. +
  5476. + break;
  5477. + }
  5478. + case TOUCH_SENSOR_CLEAR_MEM_WINDOW_RSP: {
  5479. + struct touch_sensor_set_mode_cmd_data sensor_mode_cmd;
  5480. +
  5481. + if (rsp_status != TOUCH_STATUS_TIMEOUT && rsp_status != 0) {
  5482. + rsp_failed(ipts, cmd, rsp_status);
  5483. + break;
  5484. + }
  5485. +
  5486. + if (ipts_get_state(ipts) == IPTS_STA_STOPPING)
  5487. + break;
  5488. +
  5489. + // allocate default resource: common & hid only
  5490. + if (!ipts_is_default_resource_ready(ipts)) {
  5491. + ret = ipts_allocate_default_resource(ipts);
  5492. + if (ret)
  5493. + break;
  5494. + }
  5495. +
  5496. + if (ipts->sensor_mode == TOUCH_SENSOR_MODE_RAW_DATA &&
  5497. + !ipts_is_raw_data_resource_ready(ipts)) {
  5498. + ret = ipts_allocate_raw_data_resource(ipts);
  5499. + if (ret) {
  5500. + ipts_free_default_resource(ipts);
  5501. + break;
  5502. + }
  5503. + }
  5504. +
  5505. + ipts_set_state(ipts, IPTS_STA_RESOURCE_READY);
  5506. +
  5507. + cmd_len = sizeof(struct touch_sensor_set_mode_cmd_data);
  5508. + memset(&sensor_mode_cmd, 0, cmd_len);
  5509. +
  5510. + sensor_mode_cmd.sensor_mode = ipts->sensor_mode;
  5511. + cmd_status = ipts_handle_cmd(ipts, TOUCH_SENSOR_SET_MODE_CMD,
  5512. + &sensor_mode_cmd, cmd_len);
  5513. +
  5514. + break;
  5515. + }
  5516. + case TOUCH_SENSOR_SET_MODE_RSP: {
  5517. + struct touch_sensor_set_mem_window_cmd_data smw_cmd;
  5518. +
  5519. + if (rsp_status != 0) {
  5520. + rsp_failed(ipts, cmd, rsp_status);
  5521. + break;
  5522. + }
  5523. +
  5524. + cmd_len = sizeof(struct touch_sensor_set_mem_window_cmd_data);
  5525. + memset(&smw_cmd, 0, cmd_len);
  5526. +
  5527. + ipts_get_set_mem_window_cmd_data(ipts, &smw_cmd);
  5528. + cmd_status = ipts_handle_cmd(ipts,
  5529. + TOUCH_SENSOR_SET_MEM_WINDOW_CMD, &smw_cmd, cmd_len);
  5530. +
  5531. + break;
  5532. + }
  5533. + case TOUCH_SENSOR_SET_MEM_WINDOW_RSP: {
  5534. + if (rsp_status != 0) {
  5535. + rsp_failed(ipts, cmd, rsp_status);
  5536. + break;
  5537. + }
  5538. +
  5539. + cmd_status = ipts_send_sensor_hid_ready_for_data_cmd(ipts);
  5540. + if (cmd_status)
  5541. + break;
  5542. +
  5543. + if (ipts->sensor_mode == TOUCH_SENSOR_MODE_HID)
  5544. + ipts_set_state(ipts, IPTS_STA_HID_STARTED);
  5545. + else if (ipts->sensor_mode == TOUCH_SENSOR_MODE_RAW_DATA)
  5546. + ipts_set_state(ipts, IPTS_STA_RAW_DATA_STARTED);
  5547. +
  5548. + ipts_dbg(ipts, "touch enabled %d\n", ipts_get_state(ipts));
  5549. +
  5550. + break;
  5551. + }
  5552. + case TOUCH_SENSOR_HID_READY_FOR_DATA_RSP: {
  5553. + struct touch_sensor_hid_ready_for_data_rsp_data *hid_data;
  5554. + enum ipts_state state;
  5555. +
  5556. + if (rsp_status != TOUCH_STATUS_SENSOR_DISABLED &&
  5557. + rsp_status != 0) {
  5558. + rsp_failed(ipts, cmd, rsp_status);
  5559. + break;
  5560. + }
  5561. +
  5562. + state = ipts_get_state(ipts);
  5563. + if (ipts->sensor_mode == TOUCH_SENSOR_MODE_HID &&
  5564. + state == IPTS_STA_HID_STARTED) {
  5565. + hid_data =
  5566. + &m2h_msg->m2h_data.hid_ready_for_data_rsp_data;
  5567. +
  5568. + // HID mode only uses buffer 0
  5569. + if (hid_data->touch_data_buffer_index != 0)
  5570. + break;
  5571. +
  5572. + // handle hid data
  5573. + ipts_handle_hid_data(ipts, hid_data);
  5574. + }
  5575. +
  5576. + break;
  5577. + }
  5578. + case TOUCH_SENSOR_FEEDBACK_READY_RSP: {
  5579. + if (rsp_status != TOUCH_STATUS_COMPAT_CHECK_FAIL &&
  5580. + rsp_status != TOUCH_STATUS_INVALID_PARAMS &&
  5581. + rsp_status != 0) {
  5582. + rsp_failed(ipts, cmd, rsp_status);
  5583. + break;
  5584. + }
  5585. +
  5586. + if (m2h_msg->m2h_data.feedback_ready_rsp_data.feedback_index
  5587. + == TOUCH_HID_2_ME_BUFFER_ID)
  5588. + break;
  5589. +
  5590. + if (ipts->sensor_mode == TOUCH_SENSOR_MODE_HID)
  5591. + cmd_status = ipts_handle_cmd(ipts,
  5592. + TOUCH_SENSOR_HID_READY_FOR_DATA_CMD, NULL, 0);
  5593. +
  5594. + break;
  5595. + }
  5596. + case TOUCH_SENSOR_QUIESCE_IO_RSP: {
  5597. + enum ipts_state state;
  5598. +
  5599. + if (rsp_status != 0) {
  5600. + rsp_failed(ipts, cmd, rsp_status);
  5601. + break;
  5602. + }
  5603. +
  5604. + state = ipts_get_state(ipts);
  5605. + if (state == IPTS_STA_STOPPING && ipts->restart) {
  5606. + ipts_dbg(ipts, "restart\n");
  5607. + ipts_start(ipts);
  5608. + ipts->restart = 0;
  5609. + break;
  5610. + }
  5611. +
  5612. + break;
  5613. + }
  5614. + }
  5615. +
  5616. + // handle error in rsp_status
  5617. + if (rsp_status != 0) {
  5618. + switch (rsp_status) {
  5619. + case TOUCH_STATUS_SENSOR_EXPECTED_RESET:
  5620. + case TOUCH_STATUS_SENSOR_UNEXPECTED_RESET:
  5621. + ipts_dbg(ipts, "sensor reset %d\n", rsp_status);
  5622. + ipts_restart(ipts);
  5623. + break;
  5624. + default:
  5625. + ipts_dbg(ipts, "cmd : 0x%08x, status %d\n",
  5626. + cmd, rsp_status);
  5627. + break;
  5628. + }
  5629. + }
  5630. +
  5631. + if (cmd_status)
  5632. + ipts_restart(ipts);
  5633. +
  5634. + return ret;
  5635. +}
  5636. diff --git a/drivers/misc/ipts/msg-handler.h b/drivers/misc/ipts/msg-handler.h
  5637. new file mode 100644
  5638. index 0000000000000..eca4238adf4b1
  5639. --- /dev/null
  5640. +++ b/drivers/misc/ipts/msg-handler.h
  5641. @@ -0,0 +1,28 @@
  5642. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  5643. +/*
  5644. + *
  5645. + * Intel Precise Touch & Stylus
  5646. + * Copyright (c) 2016 Intel Corporation
  5647. + *
  5648. + */
  5649. +
  5650. +#ifndef _IPTS_MSG_HANDLER_H_
  5651. +#define _IPTS_MSG_HANDLER_H_
  5652. +
  5653. +int ipts_start(struct ipts_info *ipts);
  5654. +void ipts_stop(struct ipts_info *ipts);
  5655. +int ipts_handle_cmd(struct ipts_info *ipts, u32 cmd, void *data, int data_size);
  5656. +
  5657. +int ipts_handle_resp(struct ipts_info *ipts,
  5658. + struct touch_sensor_msg_m2h *m2h_msg, u32 msg_len);
  5659. +
  5660. +int ipts_send_feedback(struct ipts_info *ipts,
  5661. + int buffer_idx, u32 transaction_id);
  5662. +
  5663. +int ipts_handle_processed_data(struct ipts_info *ipts);
  5664. +int ipts_send_sensor_quiesce_io_cmd(struct ipts_info *ipts);
  5665. +int ipts_send_sensor_hid_ready_for_data_cmd(struct ipts_info *ipts);
  5666. +int ipts_send_sensor_clear_mem_window_cmd(struct ipts_info *ipts);
  5667. +int ipts_restart(struct ipts_info *ipts);
  5668. +
  5669. +#endif /* _IPTS_MSG_HANDLER_H */
  5670. diff --git a/drivers/misc/ipts/params.c b/drivers/misc/ipts/params.c
  5671. new file mode 100644
  5672. index 0000000000000..3ea76ca8342a9
  5673. --- /dev/null
  5674. +++ b/drivers/misc/ipts/params.c
  5675. @@ -0,0 +1,42 @@
  5676. +// SPDX-License-Identifier: GPL-2.0-or-later
  5677. +/*
  5678. + *
  5679. + * Intel Precise Touch & Stylus
  5680. + * Copyright (c) 2016 Intel Corporation
  5681. + *
  5682. + */
  5683. +
  5684. +#include <linux/moduleparam.h>
  5685. +
  5686. +#include "params.h"
  5687. +
  5688. +#define IPTS_PARAM(NAME, TYPE, PERM, DESC) \
  5689. + module_param_named(NAME, ipts_modparams.NAME, TYPE, PERM); \
  5690. + MODULE_PARM_DESC(NAME, DESC)
  5691. +
  5692. +struct ipts_params ipts_modparams = {
  5693. + .ignore_fw_fallback = false,
  5694. + .ignore_config_fallback = false,
  5695. + .ignore_companion = false,
  5696. +
  5697. + .debug = false,
  5698. + .debug_thread = false,
  5699. +};
  5700. +
  5701. +IPTS_PARAM(ignore_fw_fallback, bool, 0400,
  5702. + "Don't use the IPTS firmware fallback path. (default: false)"
  5703. +);
  5704. +IPTS_PARAM(ignore_config_fallback, bool, 0400,
  5705. + "Don't try to load the IPTS firmware config from a file. (default: false)"
  5706. +);
  5707. +IPTS_PARAM(ignore_companion, bool, 0400,
  5708. + "Don't use a companion driver to load firmware. (default: false)"
  5709. +);
  5710. +
  5711. +IPTS_PARAM(debug, bool, 0400,
  5712. + "Enable IPTS debugging output. (default: false)"
  5713. +);
  5714. +IPTS_PARAM(debug_thread, bool, 0400,
  5715. + "Periodically print the ME status into the kernel log. (default: false)"
  5716. +);
  5717. +
  5718. diff --git a/drivers/misc/ipts/params.h b/drivers/misc/ipts/params.h
  5719. new file mode 100644
  5720. index 0000000000000..c20546bacb086
  5721. --- /dev/null
  5722. +++ b/drivers/misc/ipts/params.h
  5723. @@ -0,0 +1,25 @@
  5724. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  5725. +/*
  5726. + *
  5727. + * Intel Precise Touch & Stylus
  5728. + * Copyright (c) 2016 Intel Corporation
  5729. + *
  5730. + */
  5731. +
  5732. +#ifndef _IPTS_PARAMS_H_
  5733. +#define _IPTS_PARAMS_H_
  5734. +
  5735. +#include <linux/types.h>
  5736. +
  5737. +struct ipts_params {
  5738. + bool ignore_fw_fallback;
  5739. + bool ignore_config_fallback;
  5740. + bool ignore_companion;
  5741. +
  5742. + bool debug;
  5743. + bool debug_thread;
  5744. +};
  5745. +
  5746. +extern struct ipts_params ipts_modparams;
  5747. +
  5748. +#endif // _IPTS_PARAMS_H_
  5749. diff --git a/drivers/misc/ipts/resource.c b/drivers/misc/ipts/resource.c
  5750. new file mode 100644
  5751. index 0000000000000..cfd212f2cac09
  5752. --- /dev/null
  5753. +++ b/drivers/misc/ipts/resource.c
  5754. @@ -0,0 +1,291 @@
  5755. +// SPDX-License-Identifier: GPL-2.0-or-later
  5756. +/*
  5757. + *
  5758. + * Intel Precise Touch & Stylus
  5759. + * Copyright (c) 2016 Intel Corporation
  5760. + *
  5761. + */
  5762. +
  5763. +#include <linux/dma-mapping.h>
  5764. +
  5765. +#include "ipts.h"
  5766. +#include "kernel.h"
  5767. +#include "mei-msgs.h"
  5768. +
  5769. +static void free_common_resource(struct ipts_info *ipts)
  5770. +{
  5771. + char *addr;
  5772. + struct ipts_buffer_info *feedback_buffer;
  5773. + dma_addr_t dma_addr;
  5774. + u32 buffer_size;
  5775. + int i, num_of_parallels;
  5776. +
  5777. + if (ipts->resource.me2hid_buffer) {
  5778. + devm_kfree(&ipts->cldev->dev, ipts->resource.me2hid_buffer);
  5779. + ipts->resource.me2hid_buffer = 0;
  5780. + }
  5781. +
  5782. + addr = ipts->resource.hid2me_buffer.addr;
  5783. + dma_addr = ipts->resource.hid2me_buffer.dma_addr;
  5784. + buffer_size = ipts->resource.hid2me_buffer_size;
  5785. +
  5786. + if (ipts->resource.hid2me_buffer.addr) {
  5787. + dmam_free_coherent(&ipts->cldev->dev, buffer_size,
  5788. + addr, dma_addr);
  5789. +
  5790. + ipts->resource.hid2me_buffer.addr = 0;
  5791. + ipts->resource.hid2me_buffer.dma_addr = 0;
  5792. + ipts->resource.hid2me_buffer_size = 0;
  5793. + }
  5794. +
  5795. + feedback_buffer = ipts->resource.feedback_buffer;
  5796. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  5797. + for (i = 0; i < num_of_parallels; i++) {
  5798. +
  5799. + if (!feedback_buffer[i].addr)
  5800. + continue;
  5801. +
  5802. + dmam_free_coherent(&ipts->cldev->dev,
  5803. + ipts->device_info.feedback_size,
  5804. + feedback_buffer[i].addr, feedback_buffer[i].dma_addr);
  5805. +
  5806. + feedback_buffer[i].addr = 0;
  5807. + feedback_buffer[i].dma_addr = 0;
  5808. + }
  5809. +}
  5810. +
  5811. +static int allocate_common_resource(struct ipts_info *ipts)
  5812. +{
  5813. + char *addr, *me2hid_addr;
  5814. + struct ipts_buffer_info *feedback_buffer;
  5815. + dma_addr_t dma_addr;
  5816. + int i, ret = 0, num_of_parallels;
  5817. + u32 buffer_size;
  5818. +
  5819. + buffer_size = ipts->device_info.feedback_size;
  5820. +
  5821. + addr = dmam_alloc_coherent(&ipts->cldev->dev, buffer_size, &dma_addr,
  5822. + GFP_ATOMIC | __GFP_ZERO);
  5823. + if (addr == NULL)
  5824. + return -ENOMEM;
  5825. +
  5826. + me2hid_addr = devm_kzalloc(&ipts->cldev->dev, buffer_size, GFP_KERNEL);
  5827. + if (me2hid_addr == NULL) {
  5828. + ret = -ENOMEM;
  5829. + goto release_resource;
  5830. + }
  5831. +
  5832. + ipts->resource.hid2me_buffer.addr = addr;
  5833. + ipts->resource.hid2me_buffer.dma_addr = dma_addr;
  5834. + ipts->resource.hid2me_buffer_size = buffer_size;
  5835. + ipts->resource.me2hid_buffer = me2hid_addr;
  5836. +
  5837. + feedback_buffer = ipts->resource.feedback_buffer;
  5838. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  5839. +
  5840. + for (i = 0; i < num_of_parallels; i++) {
  5841. + feedback_buffer[i].addr = dmam_alloc_coherent(&ipts->cldev->dev,
  5842. + ipts->device_info.feedback_size,
  5843. + &feedback_buffer[i].dma_addr, GFP_ATOMIC|__GFP_ZERO);
  5844. +
  5845. + if (feedback_buffer[i].addr == NULL) {
  5846. + ret = -ENOMEM;
  5847. + goto release_resource;
  5848. + }
  5849. + }
  5850. +
  5851. + return 0;
  5852. +
  5853. +release_resource:
  5854. + free_common_resource(ipts);
  5855. +
  5856. + return ret;
  5857. +}
  5858. +
  5859. +void ipts_free_raw_data_resource(struct ipts_info *ipts)
  5860. +{
  5861. + if (ipts_is_raw_data_resource_ready(ipts)) {
  5862. + ipts->resource.raw_data_resource_ready = false;
  5863. + ipts_release_kernels(ipts);
  5864. + }
  5865. +}
  5866. +
  5867. +static int allocate_hid_resource(struct ipts_info *ipts)
  5868. +{
  5869. + struct ipts_buffer_info *buffer_hid;
  5870. +
  5871. + // hid mode uses only one touch data buffer
  5872. + buffer_hid = &ipts->resource.touch_data_buffer_hid;
  5873. + buffer_hid->addr = dmam_alloc_coherent(&ipts->cldev->dev,
  5874. + ipts->device_info.frame_size, &buffer_hid->dma_addr,
  5875. + GFP_ATOMIC|__GFP_ZERO);
  5876. +
  5877. + if (buffer_hid->addr == NULL)
  5878. + return -ENOMEM;
  5879. +
  5880. + return 0;
  5881. +}
  5882. +
  5883. +static void free_hid_resource(struct ipts_info *ipts)
  5884. +{
  5885. + struct ipts_buffer_info *buffer_hid;
  5886. +
  5887. + buffer_hid = &ipts->resource.touch_data_buffer_hid;
  5888. + if (buffer_hid->addr) {
  5889. + dmam_free_coherent(&ipts->cldev->dev,
  5890. + ipts->device_info.frame_size,
  5891. + buffer_hid->addr, buffer_hid->dma_addr);
  5892. +
  5893. + buffer_hid->addr = 0;
  5894. + buffer_hid->dma_addr = 0;
  5895. + }
  5896. +}
  5897. +
  5898. +int ipts_allocate_default_resource(struct ipts_info *ipts)
  5899. +{
  5900. + int ret;
  5901. +
  5902. + ret = allocate_common_resource(ipts);
  5903. + if (ret) {
  5904. + ipts_dbg(ipts, "cannot allocate common resource\n");
  5905. + return ret;
  5906. + }
  5907. +
  5908. + ret = allocate_hid_resource(ipts);
  5909. + if (ret) {
  5910. + ipts_dbg(ipts, "cannot allocate hid resource\n");
  5911. + free_common_resource(ipts);
  5912. + return ret;
  5913. + }
  5914. +
  5915. + ipts->resource.default_resource_ready = true;
  5916. +
  5917. + return 0;
  5918. +}
  5919. +
  5920. +void ipts_free_default_resource(struct ipts_info *ipts)
  5921. +{
  5922. + if (ipts_is_default_resource_ready(ipts)) {
  5923. + ipts->resource.default_resource_ready = false;
  5924. + free_hid_resource(ipts);
  5925. + free_common_resource(ipts);
  5926. + }
  5927. +}
  5928. +
  5929. +int ipts_allocate_raw_data_resource(struct ipts_info *ipts)
  5930. +{
  5931. + int ret = 0;
  5932. +
  5933. + ret = ipts_init_kernels(ipts);
  5934. + if (ret)
  5935. + return ret;
  5936. +
  5937. + ipts->resource.raw_data_resource_ready = true;
  5938. + return 0;
  5939. +}
  5940. +
  5941. +static void get_hid_only_smw_cmd_data(struct ipts_info *ipts,
  5942. + struct touch_sensor_set_mem_window_cmd_data *data,
  5943. + struct ipts_resource *resrc)
  5944. +{
  5945. + struct ipts_buffer_info *touch_buf;
  5946. + struct ipts_buffer_info *feedback_buf;
  5947. +
  5948. + touch_buf = &resrc->touch_data_buffer_hid;
  5949. + feedback_buf = &resrc->feedback_buffer[0];
  5950. +
  5951. + data->touch_data_buffer_addr_lower[0] =
  5952. + lower_32_bits(touch_buf->dma_addr);
  5953. +
  5954. + data->touch_data_buffer_addr_upper[0] =
  5955. + upper_32_bits(touch_buf->dma_addr);
  5956. +
  5957. + data->feedback_buffer_addr_lower[0] =
  5958. + lower_32_bits(feedback_buf->dma_addr);
  5959. +
  5960. + data->feedback_buffer_addr_upper[0] =
  5961. + upper_32_bits(feedback_buf->dma_addr);
  5962. +}
  5963. +
  5964. +static void get_raw_data_only_smw_cmd_data(struct ipts_info *ipts,
  5965. + struct touch_sensor_set_mem_window_cmd_data *data,
  5966. + struct ipts_resource *resrc)
  5967. +{
  5968. + u64 wq_tail_phy_addr;
  5969. + u64 cookie_phy_addr;
  5970. + struct ipts_buffer_info *touch_buf;
  5971. + struct ipts_buffer_info *feedback_buf;
  5972. + int i, num_of_parallels;
  5973. +
  5974. + touch_buf = resrc->touch_data_buffer_raw;
  5975. + feedback_buf = resrc->feedback_buffer;
  5976. +
  5977. + num_of_parallels = ipts_get_num_of_parallel_buffers(ipts);
  5978. + for (i = 0; i < num_of_parallels; i++) {
  5979. + data->touch_data_buffer_addr_lower[i] =
  5980. + lower_32_bits(touch_buf[i].dma_addr);
  5981. +
  5982. + data->touch_data_buffer_addr_upper[i] =
  5983. + upper_32_bits(touch_buf[i].dma_addr);
  5984. +
  5985. + data->feedback_buffer_addr_lower[i] =
  5986. + lower_32_bits(feedback_buf[i].dma_addr);
  5987. +
  5988. + data->feedback_buffer_addr_upper[i] =
  5989. + upper_32_bits(feedback_buf[i].dma_addr);
  5990. + }
  5991. +
  5992. + wq_tail_phy_addr = resrc->wq_info.wq_tail_phy_addr;
  5993. + data->tail_offset_addr_lower = lower_32_bits(wq_tail_phy_addr);
  5994. + data->tail_offset_addr_upper = upper_32_bits(wq_tail_phy_addr);
  5995. +
  5996. + cookie_phy_addr = resrc->wq_info.db_phy_addr +
  5997. + resrc->wq_info.db_cookie_offset;
  5998. +
  5999. + data->doorbell_cookie_addr_lower = lower_32_bits(cookie_phy_addr);
  6000. + data->doorbell_cookie_addr_upper = upper_32_bits(cookie_phy_addr);
  6001. + data->work_queue_size = resrc->wq_info.wq_size;
  6002. + data->work_queue_item_size = resrc->wq_item_size;
  6003. +}
  6004. +
  6005. +void ipts_get_set_mem_window_cmd_data(struct ipts_info *ipts,
  6006. + struct touch_sensor_set_mem_window_cmd_data *data)
  6007. +{
  6008. + struct ipts_resource *resrc = &ipts->resource;
  6009. +
  6010. + if (ipts->sensor_mode == TOUCH_SENSOR_MODE_RAW_DATA)
  6011. + get_raw_data_only_smw_cmd_data(ipts, data, resrc);
  6012. + else if (ipts->sensor_mode == TOUCH_SENSOR_MODE_HID)
  6013. + get_hid_only_smw_cmd_data(ipts, data, resrc);
  6014. +
  6015. + // hid2me is common for "raw data" and "hid"
  6016. + data->hid2me_buffer_addr_lower =
  6017. + lower_32_bits(resrc->hid2me_buffer.dma_addr);
  6018. +
  6019. + data->hid2me_buffer_addr_upper =
  6020. + upper_32_bits(resrc->hid2me_buffer.dma_addr);
  6021. +
  6022. + data->hid2me_buffer_size = resrc->hid2me_buffer_size;
  6023. +}
  6024. +
  6025. +void ipts_set_input_buffer(struct ipts_info *ipts, int parallel_idx,
  6026. + u8 *cpu_addr, u64 dma_addr)
  6027. +{
  6028. + struct ipts_buffer_info *touch_buf;
  6029. +
  6030. + touch_buf = ipts->resource.touch_data_buffer_raw;
  6031. + touch_buf[parallel_idx].dma_addr = dma_addr;
  6032. + touch_buf[parallel_idx].addr = cpu_addr;
  6033. +}
  6034. +
  6035. +void ipts_set_output_buffer(struct ipts_info *ipts, int parallel_idx,
  6036. + int output_idx, u8 *cpu_addr, u64 dma_addr)
  6037. +{
  6038. + struct ipts_buffer_info *output_buf;
  6039. +
  6040. + output_buf = &ipts->resource.raw_data_mode_output_buffer
  6041. + [parallel_idx][output_idx];
  6042. +
  6043. + output_buf->dma_addr = dma_addr;
  6044. + output_buf->addr = cpu_addr;
  6045. +}
  6046. diff --git a/drivers/misc/ipts/resource.h b/drivers/misc/ipts/resource.h
  6047. new file mode 100644
  6048. index 0000000000000..27b9c17fcb89a
  6049. --- /dev/null
  6050. +++ b/drivers/misc/ipts/resource.h
  6051. @@ -0,0 +1,26 @@
  6052. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  6053. +/*
  6054. + *
  6055. + * Intel Precise Touch & Stylus
  6056. + * Copyright (c) 2016 Intel Corporation
  6057. + *
  6058. + */
  6059. +
  6060. +#ifndef _IPTS_RESOURCE_H_
  6061. +#define _IPTS_RESOURCE_H_
  6062. +
  6063. +int ipts_allocate_default_resource(struct ipts_info *ipts);
  6064. +void ipts_free_default_resource(struct ipts_info *ipts);
  6065. +int ipts_allocate_raw_data_resource(struct ipts_info *ipts);
  6066. +void ipts_free_raw_data_resource(struct ipts_info *ipts);
  6067. +
  6068. +void ipts_get_set_mem_window_cmd_data(struct ipts_info *ipts,
  6069. + struct touch_sensor_set_mem_window_cmd_data *data);
  6070. +
  6071. +void ipts_set_input_buffer(struct ipts_info *ipts, int parallel_idx,
  6072. + u8 *cpu_addr, u64 dma_addr);
  6073. +
  6074. +void ipts_set_output_buffer(struct ipts_info *ipts, int parallel_idx,
  6075. + int output_idx, u8 *cpu_addr, u64 dma_addr);
  6076. +
  6077. +#endif // _IPTS_RESOURCE_H_
  6078. diff --git a/drivers/misc/ipts/sensor-regs.h b/drivers/misc/ipts/sensor-regs.h
  6079. new file mode 100644
  6080. index 0000000000000..c1afab48249b7
  6081. --- /dev/null
  6082. +++ b/drivers/misc/ipts/sensor-regs.h
  6083. @@ -0,0 +1,834 @@
  6084. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  6085. +/*
  6086. + *
  6087. + * Intel Precise Touch & Stylus
  6088. + * Copyright (c) 2013-2016 Intel Corporation
  6089. + *
  6090. + */
  6091. +
  6092. +#ifndef _IPTS_SENSOR_REGS_H_
  6093. +#define _IPTS_SENSOR_REGS_H_
  6094. +
  6095. +#include <linux/build_bug.h>
  6096. +
  6097. +#pragma pack(1)
  6098. +
  6099. +// Define static_assert macro (which will be available after 5.1
  6100. +// and not available on 4.19 yet) to check structure size and fail
  6101. +// compile for unexpected mismatch.
  6102. +// Taken from upstream commit 6bab69c65013bed5fce9f101a64a84d0385b3946.
  6103. +#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr)
  6104. +#define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
  6105. +
  6106. +/*
  6107. + * Compatibility versions for this header file
  6108. + */
  6109. +#define TOUCH_EDS_REV_MINOR 0
  6110. +#define TOUCH_EDS_REV_MAJOR 1
  6111. +#define TOUCH_EDS_INTF_REV 1
  6112. +#define TOUCH_PROTOCOL_VER 0
  6113. +
  6114. +/*
  6115. + * Offset 00h: TOUCH_STS: Status Register
  6116. + * This register is read by the SPI Controller immediately following
  6117. + * an interrupt.
  6118. + */
  6119. +#define TOUCH_STS_REG_OFFSET 0x00
  6120. +
  6121. +#define TOUCH_SYNC_BYTE_VALUE 0x5A
  6122. +
  6123. +/*
  6124. + * Offset 04h: TOUCH_FRAME_CHAR: Frame Characteristics Register
  6125. + * This registers describes the characteristics of each data frame read by the
  6126. + * SPI Controller in response to a touch interrupt.
  6127. + */
  6128. +#define TOUCH_FRAME_CHAR_REG_OFFSET 0x04
  6129. +
  6130. +/*
  6131. + * Offset 08h: Touch Error Register
  6132. + */
  6133. +#define TOUCH_ERR_REG_OFFSET 0x08
  6134. +
  6135. +/*
  6136. + * Offset 10h: Touch Identification Register
  6137. + */
  6138. +#define TOUCH_ID_REG_OFFSET 0x10
  6139. +#define TOUCH_ID_REG_VALUE 0x43495424
  6140. +
  6141. +/*
  6142. + * Offset 14h: TOUCH_DATA_SZ: Touch Data Size Register
  6143. + * This register describes the maximum size of frames and feedback data
  6144. + */
  6145. +#define TOUCH_DATA_SZ_REG_OFFSET 0x14
  6146. +
  6147. +#define TOUCH_MAX_FRAME_SIZE_INCREMENT 64
  6148. +#define TOUCH_MAX_FEEDBACK_SIZE_INCREMENT 64
  6149. +
  6150. +/*
  6151. + * Max allowed frame size 32KB
  6152. + * Max allowed feedback size 16KB
  6153. + */
  6154. +#define TOUCH_SENSOR_MAX_FRAME_SIZE (32 * 1024)
  6155. +#define TOUCH_SENSOR_MAX_FEEDBACK_SIZE (16 * 1024)
  6156. +
  6157. +/*
  6158. + * Offset 18h: TOUCH_CAPABILITIES: Touch Capabilities Register
  6159. + * This register informs the host as to the capabilities of the touch IC.
  6160. + */
  6161. +#define TOUCH_CAPS_REG_OFFSET 0x18
  6162. +
  6163. +#define TOUCH_BULK_DATA_MAX_WRITE_INCREMENT 64
  6164. +
  6165. +/*
  6166. + * Offset 1Ch: TOUCH_CFG: Touch Configuration Register
  6167. + * This register allows the SPI Controller to configure the touch sensor as
  6168. + * needed during touch operations.
  6169. + */
  6170. +#define TOUCH_CFG_REG_OFFSET 0x1C
  6171. +
  6172. +/*
  6173. + * Offset 20h: TOUCH_CMD: Touch Command Register
  6174. + * This register is used for sending commands to the Touch IC.
  6175. + */
  6176. +#define TOUCH_CMD_REG_OFFSET 0x20
  6177. +
  6178. +/*
  6179. + * Offset 24h: Power Management Control
  6180. + * This register is used for active power management. The Touch IC is allowed
  6181. + * to mover from Doze or Armed to Sensing after a touch has occurred. All other
  6182. + * transitions will be made at the request of the SPI Controller.
  6183. + */
  6184. +#define TOUCH_PWR_MGMT_CTRL_REG_OFFSET 0x24
  6185. +
  6186. +/*
  6187. + * Offset 28h: Vendor HW Information Register
  6188. + * This register is used to relay Intel-assigned vendor ID information to the
  6189. + * SPI Controller, which may be forwarded to SW running on the host CPU.
  6190. + */
  6191. +#define TOUCH_VEN_HW_INFO_REG_OFFSET 0x28
  6192. +
  6193. +/*
  6194. + * Offset 2Ch: HW Revision ID Register
  6195. + * This register is used to relay vendor HW revision information to the SPI
  6196. + * Controller which may be forwarded to SW running on the host CPU.
  6197. + */
  6198. +#define TOUCH_HW_REV_REG_OFFSET 0x2C
  6199. +
  6200. +/*
  6201. + * Offset 30h: FW Revision ID Register
  6202. + * This register is used to relay vendor FW revision information to the SPI
  6203. + * Controller which may be forwarded to SW running on the host CPU.
  6204. + */
  6205. +#define TOUCH_FW_REV_REG_OFFSET 0x30
  6206. +
  6207. +/*
  6208. + * Offset 34h: Compatibility Revision ID Register
  6209. + * This register is used to relay vendor compatibility information to the SPI
  6210. + * Controller which may be forwarded to SW running on the host CPU.
  6211. + * Compatibility Information is a numeric value given by Intel to the Touch IC
  6212. + * vendor based on the major and minor revision of the EDS supported. From a
  6213. + * nomenclature point of view in an x.y revision number of the EDS, the major
  6214. + * version is the value of x and the minor version is the value of y. For
  6215. + * example, a Touch IC supporting an EDS version of 0.61 would contain a major
  6216. + * version of 0 and a minor version of 61 in the register.
  6217. + */
  6218. +#define TOUCH_COMPAT_REV_REG_OFFSET 0x34
  6219. +
  6220. +/*
  6221. + * Touch Register Block is the full set of registers from offset 0x00h to 0x3F
  6222. + * This is the entire set of registers needed for normal touch operation. It
  6223. + * does not include test registers such as TOUCH_TEST_CTRL_REG
  6224. + */
  6225. +#define TOUCH_REG_BLOCK_OFFSET TOUCH_STS_REG_OFFSET
  6226. +
  6227. +/*
  6228. + * Offset 40h: Test Control Register
  6229. + * This register
  6230. + */
  6231. +#define TOUCH_TEST_CTRL_REG_OFFSET 0x40
  6232. +
  6233. +/*
  6234. + * Offsets 0x000 to 0xFFF are reserved for Intel-defined Registers
  6235. + */
  6236. +#define TOUCH_REGISTER_LIMIT 0xFFF
  6237. +
  6238. +/*
  6239. + * Data Window: Address 0x1000-0x1FFFF
  6240. + * The data window is reserved for writing and reading large quantities of
  6241. + * data to and from the sensor.
  6242. + */
  6243. +#define TOUCH_DATA_WINDOW_OFFSET 0x1000
  6244. +#define TOUCH_DATA_WINDOW_LIMIT 0x1FFFF
  6245. +
  6246. +#define TOUCH_SENSOR_MAX_OFFSET TOUCH_DATA_WINDOW_LIMIT
  6247. +
  6248. +enum touch_sts_reg_int_type {
  6249. + // Touch Data Available
  6250. + TOUCH_STS_REG_INT_TYPE_DATA_AVAIL = 0,
  6251. +
  6252. + // Reset Occurred
  6253. + TOUCH_STS_REG_INT_TYPE_RESET_OCCURRED,
  6254. +
  6255. + // Error Occurred
  6256. + TOUCH_STS_REG_INT_TYPE_ERROR_OCCURRED,
  6257. +
  6258. + // Vendor specific data, treated same as raw frame
  6259. + TOUCH_STS_REG_INT_TYPE_VENDOR_DATA,
  6260. +
  6261. + // Get Features response data available
  6262. + TOUCH_STS_REG_INT_TYPE_GET_FEATURES,
  6263. +
  6264. + TOUCH_STS_REG_INT_TYPE_MAX
  6265. +};
  6266. +static_assert(sizeof(enum touch_sts_reg_int_type) == 4);
  6267. +
  6268. +enum touch_sts_reg_pwr_state {
  6269. + // Sleep
  6270. + TOUCH_STS_REG_PWR_STATE_SLEEP = 0,
  6271. +
  6272. + // Doze
  6273. + TOUCH_STS_REG_PWR_STATE_DOZE,
  6274. +
  6275. + // Armed
  6276. + TOUCH_STS_REG_PWR_STATE_ARMED,
  6277. +
  6278. + // Sensing
  6279. + TOUCH_STS_REG_PWR_STATE_SENSING,
  6280. +
  6281. + TOUCH_STS_REG_PWR_STATE_MAX
  6282. +};
  6283. +static_assert(sizeof(enum touch_sts_reg_pwr_state) == 4);
  6284. +
  6285. +enum touch_sts_reg_init_state {
  6286. + // Ready for normal operation
  6287. + TOUCH_STS_REG_INIT_STATE_READY_FOR_OP = 0,
  6288. +
  6289. + // Touch IC needs its Firmware loaded
  6290. + TOUCH_STS_REG_INIT_STATE_FW_NEEDED,
  6291. +
  6292. + // Touch IC needs its Data loaded
  6293. + TOUCH_STS_REG_INIT_STATE_DATA_NEEDED,
  6294. +
  6295. + // Error info in TOUCH_ERR_REG
  6296. + TOUCH_STS_REG_INIT_STATE_INIT_ERROR,
  6297. +
  6298. + TOUCH_STS_REG_INIT_STATE_MAX
  6299. +};
  6300. +static_assert(sizeof(enum touch_sts_reg_init_state) == 4);
  6301. +
  6302. +union touch_sts_reg {
  6303. + u32 reg_value;
  6304. + struct {
  6305. + // When set, this indicates the hardware has data
  6306. + // that needs to be read.
  6307. + u32 int_status:1;
  6308. +
  6309. + // see TOUCH_STS_REG_INT_TYPE
  6310. + u32 int_type:4;
  6311. +
  6312. + // see TOUCH_STS_REG_PWR_STATE
  6313. + u32 pwr_state:2;
  6314. +
  6315. + // see TOUCH_STS_REG_INIT_STATE
  6316. + u32 init_state:2;
  6317. +
  6318. + // Busy bit indicates that sensor cannot
  6319. + // accept writes at this time
  6320. + u32 busy:1;
  6321. +
  6322. + // Reserved
  6323. + u32 reserved:14;
  6324. +
  6325. + // Synchronization bit, should always be TOUCH_SYNC_BYTE_VALUE
  6326. + u32 sync_byte:8;
  6327. + } fields;
  6328. +};
  6329. +static_assert(sizeof(union touch_sts_reg) == 4);
  6330. +
  6331. +union touch_frame_char_reg {
  6332. + u32 reg_value;
  6333. + struct {
  6334. + // Micro-Frame Size (MFS): Indicates the size of a touch
  6335. + // micro-frame in byte increments. When a micro-frame is to be
  6336. + // read for processing (in data mode), this is the total number
  6337. + // of bytes that must be read per interrupt, split into
  6338. + // multiple read commands no longer than RPS.
  6339. + // Maximum micro-frame size is 256KB.
  6340. + u32 microframe_size:18;
  6341. +
  6342. + // Micro-Frames per Frame (MFPF): Indicates the number of
  6343. + // micro-frames per frame. If a sensor's frame does not contain
  6344. + // micro-frames this value will be 1. Valid values are 1-31.
  6345. + u32 microframes_per_frame:5;
  6346. +
  6347. + // Micro-Frame Index (MFI): Indicates the index of the
  6348. + // micro-frame within a frame. This allows the SPI Controller
  6349. + // to maintain synchronization with the sensor and determine
  6350. + // when the final micro-frame has arrived.
  6351. + // Valid values are 1-31.
  6352. + u32 microframe_index:5;
  6353. +
  6354. + // HID/Raw Data: This bit describes whether the data from the
  6355. + // sensor is Raw data or a HID report. When set, the data
  6356. + // is a HID report.
  6357. + u32 hid_report:1;
  6358. +
  6359. + // Reserved
  6360. + u32 reserved:3;
  6361. + } fields;
  6362. +};
  6363. +static_assert(sizeof(union touch_frame_char_reg) == 4);
  6364. +
  6365. +// bit definition is vendor specific
  6366. +union touch_err_reg {
  6367. + u32 reg_value;
  6368. + struct {
  6369. + u32 invalid_fw:1;
  6370. + u32 invalid_data:1;
  6371. + u32 self_test_failed:1;
  6372. + u32 reserved:12;
  6373. + u32 fatal_error:1;
  6374. + u32 vendor_errors:16;
  6375. + } fields;
  6376. +};
  6377. +static_assert(sizeof(union touch_err_reg) == 4);
  6378. +
  6379. +union touch_data_sz_reg {
  6380. + u32 reg_value;
  6381. + struct {
  6382. + // This value describes the maximum frame size in
  6383. + // 64byte increments.
  6384. + u32 max_frame_size:12;
  6385. +
  6386. + // This value describes the maximum feedback size in
  6387. + // 64byte increments.
  6388. + u32 max_feedback_size:8;
  6389. +
  6390. + // Reserved
  6391. + u32 reserved:12;
  6392. + } fields;
  6393. +};
  6394. +static_assert(sizeof(union touch_data_sz_reg) == 4);
  6395. +
  6396. +enum touch_caps_reg_read_delay_time {
  6397. + TOUCH_CAPS_REG_READ_DELAY_TIME_0,
  6398. + TOUCH_CAPS_REG_READ_DELAY_TIME_10uS,
  6399. + TOUCH_CAPS_REG_READ_DELAY_TIME_50uS,
  6400. + TOUCH_CAPS_REG_READ_DELAY_TIME_100uS,
  6401. + TOUCH_CAPS_REG_READ_DELAY_TIME_150uS,
  6402. + TOUCH_CAPS_REG_READ_DELAY_TIME_250uS,
  6403. + TOUCH_CAPS_REG_READ_DELAY_TIME_500uS,
  6404. + TOUCH_CAPS_REG_READ_DELAY_TIME_1mS,
  6405. +};
  6406. +static_assert(sizeof(enum touch_caps_reg_read_delay_time) == 4);
  6407. +
  6408. +union touch_caps_reg {
  6409. + u32 reg_value;
  6410. + struct {
  6411. + // Reserved for future frequency
  6412. + u32 reserved0:1;
  6413. +
  6414. + // 17 MHz (14 MHz on Atom) Supported
  6415. + // 0b - Not supported, 1b - Supported
  6416. + u32 supported_17Mhz:1;
  6417. +
  6418. + // 30 MHz (25MHz on Atom) Supported
  6419. + // 0b - Not supported, 1b - Supported
  6420. + u32 supported_30Mhz:1;
  6421. +
  6422. + // 50 MHz Supported
  6423. + // 0b - Not supported, 1b - Supported
  6424. + u32 supported_50Mhz:1;
  6425. +
  6426. + // Reserved
  6427. + u32 reserved1:4;
  6428. +
  6429. + // Single I/O Supported
  6430. + // 0b - Not supported, 1b - Supported
  6431. + u32 supported_single_io:1;
  6432. +
  6433. + // Dual I/O Supported
  6434. + // 0b - Not supported, 1b - Supported
  6435. + u32 supported_dual_io:1;
  6436. +
  6437. + // Quad I/O Supported
  6438. + // 0b - Not supported, 1b - Supported
  6439. + u32 supported_quad_io:1;
  6440. +
  6441. + // Bulk Data Area Max Write Size: The amount of data the SPI
  6442. + // Controller can write to the bulk data area before it has to
  6443. + // poll the busy bit. This field is in multiples of 64 bytes.
  6444. + // The SPI Controller will write the amount of data specified
  6445. + // in this field, then check and wait for the Status.Busy bit
  6446. + // to be zero before writing the next data chunk. This field is
  6447. + // 6 bits long, allowing for 4KB of contiguous writes w/o a
  6448. + // poll of the busy bit. If this field is 0x00 the Touch IC has
  6449. + // no limit in the amount of data the SPI Controller can write
  6450. + // to the bulk data area.
  6451. + u32 bulk_data_max_write:6;
  6452. +
  6453. + // Read Delay Timer Value: This field describes the delay the
  6454. + // SPI Controller will initiate when a read interrupt follows
  6455. + // a write data command. Uses values from
  6456. + // TOUCH_CAPS_REG_READ_DELAY_TIME
  6457. + u32 read_delay_timer_value:3;
  6458. +
  6459. + // Reserved
  6460. + u32 reserved2:4;
  6461. +
  6462. + // Maximum Touch Points: A byte value based on the
  6463. + // HID descriptor definition.
  6464. + u32 max_touch_points:8;
  6465. + } fields;
  6466. +};
  6467. +static_assert(sizeof(union touch_caps_reg) == 4);
  6468. +
  6469. +enum touch_cfg_reg_bulk_xfer_size {
  6470. + // Bulk Data Transfer Size is 4 bytes
  6471. + TOUCH_CFG_REG_BULK_XFER_SIZE_4B = 0,
  6472. +
  6473. + // Bulk Data Transfer Size is 8 bytes
  6474. + TOUCH_CFG_REG_BULK_XFER_SIZE_8B,
  6475. +
  6476. + // Bulk Data Transfer Size is 16 bytes
  6477. + TOUCH_CFG_REG_BULK_XFER_SIZE_16B,
  6478. +
  6479. + // Bulk Data Transfer Size is 32 bytes
  6480. + TOUCH_CFG_REG_BULK_XFER_SIZE_32B,
  6481. +
  6482. + // Bulk Data Transfer Size is 64 bytes
  6483. + TOUCH_CFG_REG_BULK_XFER_SIZE_64B,
  6484. +
  6485. + TOUCH_CFG_REG_BULK_XFER_SIZE_MAX
  6486. +};
  6487. +static_assert(sizeof(enum touch_cfg_reg_bulk_xfer_size) == 4);
  6488. +
  6489. +/*
  6490. + * Frequency values used by TOUCH_CFG_REG
  6491. + * and TOUCH_SENSOR_GET_DEVICE_INFO_RSP_DATA.
  6492. + */
  6493. +enum touch_freq {
  6494. + // Reserved value
  6495. + TOUCH_FREQ_RSVD = 0,
  6496. +
  6497. + // Sensor set for 17MHz operation (14MHz on Atom)
  6498. + TOUCH_FREQ_17MHZ,
  6499. +
  6500. + // Sensor set for 30MHz operation (25MHz on Atom)
  6501. + TOUCH_FREQ_30MHZ,
  6502. +
  6503. + // Invalid value
  6504. + TOUCH_FREQ_MAX
  6505. +};
  6506. +static_assert(sizeof(enum touch_freq) == 4);
  6507. +
  6508. +union touch_cfg_reg {
  6509. + u32 reg_value;
  6510. + struct {
  6511. + // Touch Enable (TE): This bit is used as a HW semaphore for
  6512. + // the Touch IC to guarantee to the SPI Controller to that
  6513. + // (when 0) no sensing operations will occur and only the Reset
  6514. + // interrupt will be generated.
  6515. + //
  6516. + // When TE is cleared by the SPI
  6517. + // Controller:
  6518. + // - TICs must flush all output buffers
  6519. + // - TICs must De-assert any pending interrupt
  6520. + // - ME must throw away any partial frame and pending
  6521. + // interrupt must be cleared/not serviced.
  6522. + //
  6523. + // The SPI Controller will only modify the configuration of the
  6524. + // TIC when TE is cleared.
  6525. + // TE is defaulted to 0h on a power-on reset.
  6526. + u32 touch_enable:1;
  6527. +
  6528. + // Data/HID Packet Mode (DHPM)
  6529. + // Raw Data Mode: 0h, HID Packet Mode: 1h
  6530. + u32 dhpm:1;
  6531. +
  6532. + // Bulk Data Transfer Size: This field represents the amount
  6533. + // of data written to the Bulk Data Area
  6534. + // (SPI Offset 0x1000-0x2FFF) in a single SPI write protocol
  6535. + u32 bulk_xfer_size:4;
  6536. +
  6537. + // Frequency Select: Frequency for the TouchIC to run at.
  6538. + // Use values from TOUCH_FREQ
  6539. + u32 freq_select:3;
  6540. +
  6541. + // Reserved
  6542. + u32 reserved:23;
  6543. + } fields;
  6544. +};
  6545. +static_assert(sizeof(union touch_cfg_reg) == 4);
  6546. +
  6547. +enum touch_cmd_reg_code {
  6548. + // No Operation
  6549. + TOUCH_CMD_REG_CODE_NOP = 0,
  6550. +
  6551. + // Soft Reset
  6552. + TOUCH_CMD_REG_CODE_SOFT_RESET,
  6553. +
  6554. + // Prepare All Registers for Read
  6555. + TOUCH_CMD_REG_CODE_PREP_4_READ,
  6556. +
  6557. + // Generate Test Packets according to value in TOUCH_TEST_CTRL_REG
  6558. + TOUCH_CMD_REG_CODE_GEN_TEST_PACKETS,
  6559. +
  6560. + TOUCH_CMD_REG_CODE_MAX
  6561. +};
  6562. +static_assert(sizeof(enum touch_cmd_reg_code) == 4);
  6563. +
  6564. +union touch_cmd_reg {
  6565. + u32 reg_value;
  6566. + struct {
  6567. + // Command Code: See TOUCH_CMD_REG_CODE
  6568. + u32 command_code:8;
  6569. +
  6570. + // Reserved
  6571. + u32 reserved:24;
  6572. + } fields;
  6573. +};
  6574. +static_assert(sizeof(union touch_cmd_reg) == 4);
  6575. +
  6576. +enum touch_pwr_mgmt_ctrl_reg_cmd {
  6577. + // No change to power state
  6578. + TOUCH_PWR_MGMT_CTRL_REG_CMD_NOP = 0,
  6579. +
  6580. + // Sleep - set when the system goes into connected standby
  6581. + TOUCH_PWR_MGMT_CTRL_REG_CMD_SLEEP,
  6582. +
  6583. + // Doze - set after 300 seconds of inactivity
  6584. + TOUCH_PWR_MGMT_CTRL_REG_CMD_DOZE,
  6585. +
  6586. + // Armed - Set by FW when a "finger off" message is
  6587. + // received from the EUs
  6588. + TOUCH_PWR_MGMT_CTRL_REG_CMD_ARMED,
  6589. +
  6590. + // Sensing - not typically set by FW
  6591. + TOUCH_PWR_MGMT_CTRL_REG_CMD_SENSING,
  6592. +
  6593. + // Values will result in no change to the power state of the Touch IC
  6594. + TOUCH_PWR_MGMT_CTRL_REG_CMD_MAX
  6595. +};
  6596. +static_assert(sizeof(enum touch_pwr_mgmt_ctrl_reg_cmd) == 4);
  6597. +
  6598. +union touch_pwr_mgmt_ctrl_reg {
  6599. + u32 reg_value;
  6600. + struct {
  6601. + // Power State Command: See TOUCH_PWR_MGMT_CTRL_REG_CMD
  6602. + u32 pwr_state_cmd:3;
  6603. +
  6604. + // Reserved
  6605. + u32 reserved:29;
  6606. + } fields;
  6607. +};
  6608. +static_assert(sizeof(union touch_pwr_mgmt_ctrl_reg) == 4);
  6609. +
  6610. +union touch_ven_hw_info_reg {
  6611. + u32 reg_value;
  6612. + struct {
  6613. + // Touch Sensor Vendor ID
  6614. + u32 vendor_id:16;
  6615. +
  6616. + // Touch Sensor Device ID
  6617. + u32 device_id:16;
  6618. + } fields;
  6619. +};
  6620. +static_assert(sizeof(union touch_ven_hw_info_reg) == 4);
  6621. +
  6622. +union touch_compat_rev_reg {
  6623. + u32 reg_value;
  6624. +
  6625. + struct {
  6626. + // EDS Minor Revision
  6627. + u8 minor;
  6628. +
  6629. + // EDS Major Revision
  6630. + u8 major;
  6631. +
  6632. + // Interface Revision Number (from EDS)
  6633. + u8 intf_rev;
  6634. +
  6635. + // EU Kernel Compatibility Version - vendor specific value
  6636. + u8 kernel_compat_ver;
  6637. + } fields;
  6638. +};
  6639. +static_assert(sizeof(union touch_compat_rev_reg) == 4);
  6640. +
  6641. +struct touch_reg_block {
  6642. + // 0x00
  6643. + union touch_sts_reg sts_reg;
  6644. +
  6645. + // 0x04
  6646. + union touch_frame_char_reg frame_char_reg;
  6647. +
  6648. + // 0x08
  6649. + union touch_err_reg error_reg;
  6650. +
  6651. + // 0x0C
  6652. + u32 reserved0;
  6653. +
  6654. + // 0x10 - expected value is "$TIC" or 0x43495424
  6655. + u32 id_reg;
  6656. +
  6657. + // 0x14
  6658. + union touch_data_sz_reg data_size_reg;
  6659. +
  6660. + // 0x18
  6661. + union touch_caps_reg caps_reg;
  6662. +
  6663. + // 0x1C
  6664. + union touch_cfg_reg cfg_reg;
  6665. +
  6666. + // 0x20
  6667. + union touch_cmd_reg cmd_reg;
  6668. +
  6669. + // 0x24
  6670. + union touch_pwr_mgmt_ctrl_reg pwm_mgme_ctrl_reg;
  6671. +
  6672. + // 0x28
  6673. + union touch_ven_hw_info_reg ven_hw_info_reg;
  6674. +
  6675. + // 0x2C
  6676. + u32 hw_rev_reg;
  6677. +
  6678. + // 0x30
  6679. + u32 fw_rev_reg;
  6680. +
  6681. + // 0x34
  6682. + union touch_compat_rev_reg compat_rev_reg;
  6683. +
  6684. + // 0x38
  6685. + u32 reserved1;
  6686. +
  6687. + // 0x3C
  6688. + u32 reserved2;
  6689. +};
  6690. +static_assert(sizeof(struct touch_reg_block) == 64);
  6691. +
  6692. +union touch_test_ctrl_reg {
  6693. + u32 reg_value;
  6694. + struct {
  6695. + // Size of Test Frame in Raw Data Mode: This field specifies
  6696. + // the test frame size in raw data mode in multiple of 64 bytes.
  6697. + // For example, if this field value is 16, the test frame size
  6698. + // will be 16x64 = 1K.
  6699. + u32 raw_test_frame_size:16;
  6700. +
  6701. + // Number of Raw Data Frames or HID Report Packets Generation.
  6702. + // This field represents the number of test frames or HID
  6703. + // reports to be generated when test mode is enabled. When
  6704. + // multiple packets/frames are generated, they need be
  6705. + // generated at 100 Hz frequency, i.e. 10ms per packet/frame.
  6706. + u32 num_test_frames:16;
  6707. + } fields;
  6708. +};
  6709. +static_assert(sizeof(union touch_test_ctrl_reg) == 4);
  6710. +
  6711. +/*
  6712. + * The following data structures represent the headers defined in the Data
  6713. + * Structures chapter of the Intel Integrated Touch EDS
  6714. + */
  6715. +
  6716. +// Enumeration used in TOUCH_RAW_DATA_HDR
  6717. +enum touch_raw_data_types {
  6718. + TOUCH_RAW_DATA_TYPE_FRAME = 0,
  6719. +
  6720. + // RawData will be the TOUCH_ERROR struct below
  6721. + TOUCH_RAW_DATA_TYPE_ERROR,
  6722. +
  6723. + // Set when InterruptType is Vendor Data
  6724. + TOUCH_RAW_DATA_TYPE_VENDOR_DATA,
  6725. +
  6726. + TOUCH_RAW_DATA_TYPE_HID_REPORT,
  6727. + TOUCH_RAW_DATA_TYPE_GET_FEATURES,
  6728. + TOUCH_RAW_DATA_TYPE_MAX
  6729. +};
  6730. +static_assert(sizeof(enum touch_raw_data_types) == 4);
  6731. +
  6732. +// Private data structure. Kernels must copy to HID driver buffer
  6733. +struct touch_hid_private_data {
  6734. + u32 transaction_id;
  6735. + u8 reserved[28];
  6736. +};
  6737. +static_assert(sizeof(struct touch_hid_private_data) == 32);
  6738. +
  6739. +// This is the data structure sent from the PCH FW to the EU kernel
  6740. +struct touch_raw_data_hdr {
  6741. + // use values from TOUCH_RAW_DATA_TYPES
  6742. + u32 data_type;
  6743. +
  6744. + // The size in bytes of the raw data read from the sensor, does not
  6745. + // include TOUCH_RAW_DATA_HDR. Will be the sum of all uFrames, or size
  6746. + // of TOUCH_ERROR for if DataType is TOUCH_RAW_DATA_TYPE_ERROR
  6747. + u32 raw_data_size_bytes;
  6748. +
  6749. + // An ID to qualify with the feedback data to track buffer usage
  6750. + u32 buffer_id;
  6751. +
  6752. + // Must match protocol version of the EDS
  6753. + u32 protocol_ver;
  6754. +
  6755. + // Copied from the Compatibility Revision ID Reg
  6756. + u8 kernel_compat_id;
  6757. +
  6758. + // Padding to extend header to full 64 bytes and allow for growth
  6759. + u8 reserved[15];
  6760. +
  6761. + // Private data structure. Kernels must copy to HID driver buffer
  6762. + struct touch_hid_private_data hid_private_data;
  6763. +};
  6764. +static_assert(sizeof(struct touch_raw_data_hdr) == 64);
  6765. +
  6766. +struct touch_raw_data {
  6767. + struct touch_raw_data_hdr header;
  6768. +
  6769. + // used to access the raw data as an array and keep the compilers
  6770. + // happy. Actual size of this array is Header.RawDataSizeBytes
  6771. + u8 raw_data[1];
  6772. +};
  6773. +
  6774. +/*
  6775. + * The following section describes the data passed in TOUCH_RAW_DATA.RawData
  6776. + * when DataType equals TOUCH_RAW_DATA_TYPE_ERROR
  6777. + * Note: This data structure is also applied to HID mode
  6778. + */
  6779. +enum touch_err_types {
  6780. + TOUCH_RAW_DATA_ERROR = 0,
  6781. + TOUCH_RAW_ERROR_MAX
  6782. +};
  6783. +static_assert(sizeof(enum touch_err_types) == 4);
  6784. +
  6785. +union touch_me_fw_error {
  6786. + u32 value;
  6787. + struct {
  6788. + u32 invalid_frame_characteristics:1;
  6789. + u32 microframe_index_invalid:1;
  6790. + u32 reserved:30;
  6791. + } fields;
  6792. +};
  6793. +static_assert(sizeof(union touch_me_fw_error) == 4);
  6794. +
  6795. +struct touch_error {
  6796. + // This must be a value from TOUCH_ERROR_TYPES
  6797. + u8 touch_error_type;
  6798. + u8 reserved[3];
  6799. + union touch_me_fw_error touch_me_fw_error;
  6800. +
  6801. + // Contains the value copied from the Touch Error Reg
  6802. + union touch_err_reg touch_error_register;
  6803. +};
  6804. +static_assert(sizeof(struct touch_error) == 12);
  6805. +
  6806. +// Enumeration used in TOUCH_FEEDBACK_BUFFER
  6807. +enum touch_feedback_cmd_types {
  6808. + TOUCH_FEEDBACK_CMD_TYPE_NONE = 0,
  6809. + TOUCH_FEEDBACK_CMD_TYPE_SOFT_RESET,
  6810. + TOUCH_FEEDBACK_CMD_TYPE_GOTO_ARMED,
  6811. + TOUCH_FEEDBACK_CMD_TYPE_GOTO_SENSING,
  6812. + TOUCH_FEEDBACK_CMD_TYPE_GOTO_SLEEP,
  6813. + TOUCH_FEEDBACK_CMD_TYPE_GOTO_DOZE,
  6814. + TOUCH_FEEDBACK_CMD_TYPE_HARD_RESET,
  6815. + TOUCH_FEEDBACK_CMD_TYPE_MAX
  6816. +};
  6817. +static_assert(sizeof(enum touch_feedback_cmd_types) == 4);
  6818. +
  6819. +// Enumeration used in TOUCH_FEEDBACK_HDR
  6820. +enum touch_feedback_data_types {
  6821. + // This is vendor specific feedback to be written to the sensor
  6822. + TOUCH_FEEDBACK_DATA_TYPE_FEEDBACK = 0,
  6823. +
  6824. + // This is a set features command to be written to the sensor
  6825. + TOUCH_FEEDBACK_DATA_TYPE_SET_FEATURES,
  6826. +
  6827. + // This is a get features command to be written to the sensor
  6828. + TOUCH_FEEDBACK_DATA_TYPE_GET_FEATURES,
  6829. +
  6830. + // This is a HID output report to be written to the sensor
  6831. + TOUCH_FEEDBACK_DATA_TYPE_OUTPUT_REPORT,
  6832. +
  6833. + // This is calibration data to be written to system flash
  6834. + TOUCH_FEEDBACK_DATA_TYPE_STORE_DATA,
  6835. +
  6836. + TOUCH_FEEDBACK_DATA_TYPE_MAX
  6837. +};
  6838. +static_assert(sizeof(enum touch_feedback_data_types) == 4);
  6839. +
  6840. +/*
  6841. + * This is the data structure sent from the EU kernels back to the ME FW.
  6842. + * In addition to "feedback" data, the FW can execute a "command" described by
  6843. + * the command type parameter. Any payload data will always be sent to the TIC
  6844. + * first, then any command will be issued.
  6845. + */
  6846. +struct touch_feedback_hdr {
  6847. + // use values from TOUCH_FEEDBACK_CMD_TYPES
  6848. + u32 feedback_cmd_type;
  6849. +
  6850. + // The amount of data to be written to the sensor,
  6851. + // not including the header
  6852. + u32 payload_size_bytes;
  6853. +
  6854. + // The ID of the raw data buffer that generated this feedback data
  6855. + u32 buffer_id;
  6856. +
  6857. + // Must match protocol version of the EDS
  6858. + u32 protocol_ver;
  6859. +
  6860. + // use values from TOUCH_FEEDBACK_DATA_TYPES. This is not relevant
  6861. + // if PayloadSizeBytes is 0
  6862. + u32 feedback_data_type;
  6863. +
  6864. + // The offset from TOUCH_DATA_WINDOW_OFFSET at which to write the
  6865. + // Payload data. Maximum offset is 0x1EFFF.
  6866. + u32 spi_offest;
  6867. +
  6868. + // Padding to extend header to full 64 bytes and allow for growth
  6869. + u8 reserved[40];
  6870. +};
  6871. +static_assert(sizeof(struct touch_feedback_hdr) == 64);
  6872. +
  6873. +struct touch_feedback_buffer {
  6874. + struct touch_feedback_hdr Header;
  6875. +
  6876. + // used to access the feedback data as an array and keep the compilers
  6877. + // happy. Actual size of this array is Header.PayloadSizeBytes
  6878. + u8 feedback_data[1];
  6879. +};
  6880. +
  6881. +/*
  6882. + * This data structure describes the header prepended to all data
  6883. + * written to the touch IC at the bulk data write
  6884. + * (TOUCH_DATA_WINDOW_OFFSET + TOUCH_FEEDBACK_HDR.SpiOffest) address.
  6885. + */
  6886. +enum touch_write_data_type {
  6887. + TOUCH_WRITE_DATA_TYPE_FW_LOAD = 0,
  6888. + TOUCH_WRITE_DATA_TYPE_DATA_LOAD,
  6889. + TOUCH_WRITE_DATA_TYPE_FEEDBACK,
  6890. + TOUCH_WRITE_DATA_TYPE_SET_FEATURES,
  6891. + TOUCH_WRITE_DATA_TYPE_GET_FEATURES,
  6892. + TOUCH_WRITE_DATA_TYPE_OUTPUT_REPORT,
  6893. + TOUCH_WRITE_DATA_TYPE_NO_DATA_USE_DEFAULTS,
  6894. + TOUCH_WRITE_DATA_TYPE_MAX
  6895. +};
  6896. +static_assert(sizeof(enum touch_write_data_type) == 4);
  6897. +
  6898. +struct touch_write_hdr {
  6899. + // Use values from TOUCH_WRITE_DATA_TYPE
  6900. + u32 write_data_type;
  6901. +
  6902. + // This field designates the amount of data to follow
  6903. + u32 write_data_len;
  6904. +};
  6905. +static_assert(sizeof(struct touch_write_hdr) == 8);
  6906. +
  6907. +struct touch_write_data {
  6908. + struct touch_write_hdr header;
  6909. +
  6910. + // used to access the write data as an array and keep the compilers
  6911. + // happy. Actual size of this array is Header.WriteDataLen
  6912. + u8 write_data[1];
  6913. +};
  6914. +
  6915. +#pragma pack()
  6916. +
  6917. +#endif // _IPTS_SENSOR_REGS_H_
  6918. diff --git a/drivers/misc/ipts/state.h b/drivers/misc/ipts/state.h
  6919. new file mode 100644
  6920. index 0000000000000..ef73d28db47cc
  6921. --- /dev/null
  6922. +++ b/drivers/misc/ipts/state.h
  6923. @@ -0,0 +1,22 @@
  6924. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  6925. +/*
  6926. + *
  6927. + * Intel Precise Touch & Stylus
  6928. + * Copyright (c) 2016 Intel Corporation
  6929. + *
  6930. + */
  6931. +
  6932. +#ifndef _IPTS_STATE_H_
  6933. +#define _IPTS_STATE_H_
  6934. +
  6935. +// IPTS driver states
  6936. +enum ipts_state {
  6937. + IPTS_STA_NONE,
  6938. + IPTS_STA_INIT,
  6939. + IPTS_STA_RESOURCE_READY,
  6940. + IPTS_STA_HID_STARTED,
  6941. + IPTS_STA_RAW_DATA_STARTED,
  6942. + IPTS_STA_STOPPING
  6943. +};
  6944. +
  6945. +#endif // _IPTS_STATE_H_
  6946. diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
  6947. index 2ac1dc5104b7a..5daa857a49389 100644
  6948. --- a/drivers/misc/mei/hw-me-regs.h
  6949. +++ b/drivers/misc/mei/hw-me-regs.h
  6950. @@ -119,6 +119,7 @@
  6951. #define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */
  6952. #define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */
  6953. +#define MEI_DEV_ID_SPT_4 0x9D3E /* Sunrise Point 4 */
  6954. #define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */
  6955. #define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */
  6956. diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
  6957. index b4bf12f27caf5..34f4338fa6417 100644
  6958. --- a/drivers/misc/mei/pci-me.c
  6959. +++ b/drivers/misc/mei/pci-me.c
  6960. @@ -86,6 +86,7 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
  6961. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  6962. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  6963. + {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_4, MEI_ME_PCH8_CFG)},
  6964. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
  6965. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
  6966. {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
  6967. diff --git a/include/linux/ipts-binary.h b/include/linux/ipts-binary.h
  6968. new file mode 100644
  6969. index 0000000000000..98b54d74ff888
  6970. --- /dev/null
  6971. +++ b/include/linux/ipts-binary.h
  6972. @@ -0,0 +1,140 @@
  6973. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  6974. +/*
  6975. + *
  6976. + * Intel Precise Touch & Stylus
  6977. + * Copyright (c) 2016 Intel Corporation
  6978. + *
  6979. + */
  6980. +
  6981. +#ifndef IPTS_BINARY_H
  6982. +#define IPTS_BINARY_H
  6983. +
  6984. +#include <linux/ipts.h>
  6985. +#include <linux/types.h>
  6986. +
  6987. +#define IPTS_BIN_HEADER_VERSION 2
  6988. +
  6989. +#pragma pack(1)
  6990. +
  6991. +// we support 16 output buffers (1:feedback, 15:HID)
  6992. +#define MAX_NUM_OUTPUT_BUFFERS 16
  6993. +
  6994. +enum ipts_bin_res_type {
  6995. + IPTS_BIN_KERNEL,
  6996. + IPTS_BIN_RO_DATA,
  6997. + IPTS_BIN_RW_DATA,
  6998. + IPTS_BIN_SENSOR_FRAME,
  6999. + IPTS_BIN_OUTPUT,
  7000. + IPTS_BIN_DYNAMIC_STATE_HEAP,
  7001. + IPTS_BIN_PATCH_LOCATION_LIST,
  7002. + IPTS_BIN_ALLOCATION_LIST,
  7003. + IPTS_BIN_COMMAND_BUFFER_PACKET,
  7004. + IPTS_BIN_TAG,
  7005. +};
  7006. +
  7007. +struct ipts_bin_header {
  7008. + char str[4];
  7009. + u32 version;
  7010. +
  7011. +#if IPTS_BIN_HEADER_VERSION > 1
  7012. + u32 gfxcore;
  7013. + u32 revid;
  7014. +#endif
  7015. +};
  7016. +
  7017. +struct ipts_bin_alloc {
  7018. + u32 handle;
  7019. + u32 reserved;
  7020. +};
  7021. +
  7022. +struct ipts_bin_alloc_list {
  7023. + u32 num;
  7024. + struct ipts_bin_alloc alloc[];
  7025. +};
  7026. +
  7027. +struct ipts_bin_cmdbuf {
  7028. + u32 size;
  7029. + char data[];
  7030. +};
  7031. +
  7032. +struct ipts_bin_res {
  7033. + u32 handle;
  7034. + enum ipts_bin_res_type type;
  7035. + u32 initialize;
  7036. + u32 aligned_size;
  7037. + u32 size;
  7038. + char data[];
  7039. +};
  7040. +
  7041. +enum ipts_bin_io_buffer_type {
  7042. + IPTS_INPUT,
  7043. + IPTS_OUTPUT,
  7044. + IPTS_CONFIGURATION,
  7045. + IPTS_CALIBRATION,
  7046. + IPTS_FEATURE,
  7047. +};
  7048. +
  7049. +struct ipts_bin_io_header {
  7050. + char str[10];
  7051. + u16 type;
  7052. +};
  7053. +
  7054. +struct ipts_bin_res_list {
  7055. + u32 num;
  7056. + struct ipts_bin_res res[];
  7057. +};
  7058. +
  7059. +struct ipts_bin_patch {
  7060. + u32 index;
  7061. + u32 reserved1[2];
  7062. + u32 alloc_offset;
  7063. + u32 patch_offset;
  7064. + u32 reserved2;
  7065. +};
  7066. +
  7067. +struct ipts_bin_patch_list {
  7068. + u32 num;
  7069. + struct ipts_bin_patch patch[];
  7070. +};
  7071. +
  7072. +struct ipts_bin_guc_wq_info {
  7073. + u32 batch_offset;
  7074. + u32 size;
  7075. + char data[];
  7076. +};
  7077. +
  7078. +struct ipts_bin_bufid_patch {
  7079. + u32 imm_offset;
  7080. + u32 mem_offset;
  7081. +};
  7082. +
  7083. +enum ipts_bin_data_file_flags {
  7084. + IPTS_DATA_FILE_FLAG_NONE = 0,
  7085. + IPTS_DATA_FILE_FLAG_SHARE = 1,
  7086. + IPTS_DATA_FILE_FLAG_ALLOC_CONTIGUOUS = 2,
  7087. +};
  7088. +
  7089. +struct ipts_bin_data_file_info {
  7090. + u32 io_buffer_type;
  7091. + u32 flags;
  7092. + char file_name[MAX_IOCL_FILE_NAME_LEN];
  7093. +};
  7094. +
  7095. +struct ipts_bin_fw_info {
  7096. + char fw_name[MAX_IOCL_FILE_NAME_LEN];
  7097. +
  7098. + // output index. -1 for no use
  7099. + s32 vendor_output;
  7100. +
  7101. + u32 num_of_data_files;
  7102. + struct ipts_bin_data_file_info data_file[];
  7103. +};
  7104. +
  7105. +struct ipts_bin_fw_list {
  7106. + u32 num_of_fws;
  7107. + struct ipts_bin_fw_info fw_info[];
  7108. +};
  7109. +
  7110. +#pragma pack()
  7111. +
  7112. +#endif // IPTS_BINARY_H
  7113. diff --git a/include/linux/ipts-companion.h b/include/linux/ipts-companion.h
  7114. new file mode 100644
  7115. index 0000000000000..de31f5e0b186b
  7116. --- /dev/null
  7117. +++ b/include/linux/ipts-companion.h
  7118. @@ -0,0 +1,29 @@
  7119. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  7120. +/*
  7121. + *
  7122. + * Intel Precise Touch & Stylus
  7123. + * Copyright (c) 2016 Intel Corporation
  7124. + * Copyright (c) 2019 Dorian Stoll
  7125. + *
  7126. + */
  7127. +
  7128. +#ifndef IPTS_COMPANION_H
  7129. +#define IPTS_COMPANION_H
  7130. +
  7131. +#include <linux/firmware.h>
  7132. +#include <linux/ipts-binary.h>
  7133. +
  7134. +struct ipts_companion {
  7135. + int (*firmware_request)(struct ipts_companion *companion,
  7136. + const struct firmware **fw,
  7137. + const char *name, struct device *device);
  7138. +
  7139. + struct ipts_bin_fw_info **firmware_config;
  7140. + void *data;
  7141. + const char *name;
  7142. +};
  7143. +
  7144. +int ipts_add_companion(struct ipts_companion *companion);
  7145. +int ipts_remove_companion(struct ipts_companion *companion);
  7146. +
  7147. +#endif // IPTS_COMPANION_H
  7148. diff --git a/include/linux/ipts-gfx.h b/include/linux/ipts-gfx.h
  7149. new file mode 100644
  7150. index 0000000000000..cb9d98fe96e4b
  7151. --- /dev/null
  7152. +++ b/include/linux/ipts-gfx.h
  7153. @@ -0,0 +1,86 @@
  7154. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  7155. +/*
  7156. + *
  7157. + * Intel Precise Touch & Stylus
  7158. + * Copyright (c) 2016 Intel Corporation
  7159. + *
  7160. + */
  7161. +
  7162. +#ifndef IPTS_GFX_H
  7163. +#define IPTS_GFX_H
  7164. +
  7165. +enum {
  7166. + IPTS_INTERFACE_V1 = 1,
  7167. +};
  7168. +
  7169. +#define IPTS_BUF_FLAG_CONTIGUOUS 0x01
  7170. +
  7171. +#define IPTS_NOTIFY_STA_BACKLIGHT_OFF 0x00
  7172. +#define IPTS_NOTIFY_STA_BACKLIGHT_ON 0x01
  7173. +
  7174. +struct ipts_mapbuffer {
  7175. + u32 size;
  7176. + u32 flags;
  7177. + void *gfx_addr;
  7178. + void *cpu_addr;
  7179. + u64 buf_handle;
  7180. + u64 phy_addr;
  7181. +};
  7182. +
  7183. +struct ipts_wq_info {
  7184. + u64 db_addr;
  7185. + u64 db_phy_addr;
  7186. + u32 db_cookie_offset;
  7187. + u32 wq_size;
  7188. + u64 wq_addr;
  7189. + u64 wq_phy_addr;
  7190. +
  7191. + // head of wq is managed by GPU
  7192. + u64 wq_head_addr;
  7193. + u64 wq_head_phy_addr;
  7194. +
  7195. + // tail of wq is managed by CSME
  7196. + u64 wq_tail_addr;
  7197. + u64 wq_tail_phy_addr;
  7198. +};
  7199. +
  7200. +struct ipts_ops {
  7201. + int (*get_wq_info)(uint64_t gfx_handle,
  7202. + struct ipts_wq_info *wq_info);
  7203. + int (*map_buffer)(uint64_t gfx_handle,
  7204. + struct ipts_mapbuffer *mapbuffer);
  7205. + int (*unmap_buffer)(uint64_t gfx_handle, uint64_t buf_handle);
  7206. +};
  7207. +
  7208. +struct ipts_callback {
  7209. + void (*workload_complete)(void *data);
  7210. + void (*notify_gfx_status)(u32 status, void *data);
  7211. +};
  7212. +
  7213. +struct ipts_connect {
  7214. + // input: Client device for PM setup
  7215. + struct device *client;
  7216. +
  7217. + // input: Callback addresses
  7218. + struct ipts_callback ipts_cb;
  7219. +
  7220. + // input: Callback data
  7221. + void *data;
  7222. +
  7223. + // input: interface version
  7224. + u32 if_version;
  7225. +
  7226. + // output: GFX version
  7227. + u32 gfx_version;
  7228. +
  7229. + // output: GFX handle
  7230. + u64 gfx_handle;
  7231. +
  7232. + // output: GFX ops for IPTS
  7233. + struct ipts_ops ipts_ops;
  7234. +};
  7235. +
  7236. +int ipts_connect(struct ipts_connect *ipts_connect);
  7237. +void ipts_disconnect(uint64_t gfx_handle);
  7238. +
  7239. +#endif // IPTS_GFX_H
  7240. diff --git a/include/linux/ipts.h b/include/linux/ipts.h
  7241. new file mode 100644
  7242. index 0000000000000..f229a34368516
  7243. --- /dev/null
  7244. +++ b/include/linux/ipts.h
  7245. @@ -0,0 +1,19 @@
  7246. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  7247. +/*
  7248. + *
  7249. + * Intel Precise Touch & Stylus
  7250. + * Copyright (c) 2016 Intel Corporation
  7251. + *
  7252. + */
  7253. +
  7254. +#ifndef IPTS_H
  7255. +#define IPTS_H
  7256. +
  7257. +#include <linux/bits.h>
  7258. +
  7259. +#define MAX_IOCL_FILE_NAME_LEN 80
  7260. +#define MAX_IOCL_FILE_PATH_LEN 256
  7261. +
  7262. +#define IPTS_QUIRK_NONE 0
  7263. +
  7264. +#endif // IPTS_H
  7265. --
  7266. 2.27.0