|
@@ -1,7 +1,7 @@
|
|
|
-From a1e520b7f0e94ca4a0365c6fcf9cfb31b57149ac Mon Sep 17 00:00:00 2001
|
|
|
-From: Dorian Stoll <dorian.stoll@tmsp.io>
|
|
|
+From 05296f2e99a9f6c9ef6fa47e7c879c73b07c7322 Mon Sep 17 00:00:00 2001
|
|
|
+From: Maximilian Luz <luzmaximilian@gmail.com>
|
|
|
Date: Mon, 16 Sep 2019 04:10:51 +0200
|
|
|
-Subject: [PATCH 8/9] use legacy i915 driver
|
|
|
+Subject: [PATCH 8/9] legacy-i915
|
|
|
|
|
|
---
|
|
|
drivers/gpu/drm/Kconfig | 2 +-
|
|
@@ -133,7 +133,7 @@ Subject: [PATCH 8/9] use legacy i915 driver
|
|
|
drivers/gpu/drm/i915_legacy/i915_oa_sklgt4.c | 90 +
|
|
|
drivers/gpu/drm/i915_legacy/i915_oa_sklgt4.h | 15 +
|
|
|
drivers/gpu/drm/i915_legacy/i915_params.c | 237 +
|
|
|
- drivers/gpu/drm/i915_legacy/i915_params.h | 93 +
|
|
|
+ drivers/gpu/drm/i915_legacy/i915_params.h | 94 +
|
|
|
drivers/gpu/drm/i915_legacy/i915_pci.c | 957 +
|
|
|
drivers/gpu/drm/i915_legacy/i915_perf.c | 3519 ++++
|
|
|
drivers/gpu/drm/i915_legacy/i915_pmu.c | 1096 +
|
|
@@ -362,7 +362,7 @@ Subject: [PATCH 8/9] use legacy i915 driver
|
|
|
.../drm/i915_legacy/selftests/scatterlist.c | 379 +
|
|
|
drivers/gpu/drm/i915_legacy/vlv_dsi.c | 1830 ++
|
|
|
drivers/gpu/drm/i915_legacy/vlv_dsi_pll.c | 567 +
|
|
|
- 358 files changed, 244184 insertions(+), 2 deletions(-)
|
|
|
+ 358 files changed, 244185 insertions(+), 2 deletions(-)
|
|
|
create mode 100644 drivers/gpu/drm/i915_legacy/.gitignore
|
|
|
create mode 100644 drivers/gpu/drm/i915_legacy/Kconfig
|
|
|
create mode 100644 drivers/gpu/drm/i915_legacy/Kconfig.debug
|
|
@@ -4934,7 +4934,7 @@ index 000000000000..19cf1bbe059d
|
|
|
+}
|
|
|
diff --git a/drivers/gpu/drm/i915_legacy/gvt/cmd_parser.c b/drivers/gpu/drm/i915_legacy/gvt/cmd_parser.c
|
|
|
new file mode 100644
|
|
|
-index 000000000000..54abe249861d
|
|
|
+index 000000000000..de5347725564
|
|
|
--- /dev/null
|
|
|
+++ b/drivers/gpu/drm/i915_legacy/gvt/cmd_parser.c
|
|
|
@@ -0,0 +1,2998 @@
|
|
@@ -5186,16 +5186,16 @@ index 000000000000..54abe249861d
|
|
|
+#define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
|
|
|
+#define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
|
|
|
+
|
|
|
-+#define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
|
|
|
-+#define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
|
|
|
++#define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
|
|
|
++#define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
|
|
|
++#define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
|
|
|
++#define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
|
|
|
++#define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
|
|
|
++#define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
|
|
|
++#define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
|
|
|
++#define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
|
|
|
++#define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
|
|
|
++#define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
|
|
|
+#define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
|
|
|
+
|
|
|
+#define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
|
|
@@ -39236,7 +39236,7 @@ index 000000000000..d485d49c473b
|
|
|
+#endif
|
|
|
diff --git a/drivers/gpu/drm/i915_legacy/i915_drv.h b/drivers/gpu/drm/i915_legacy/i915_drv.h
|
|
|
new file mode 100644
|
|
|
-index 000000000000..bf555493e85d
|
|
|
+index 000000000000..066fd2a12851
|
|
|
--- /dev/null
|
|
|
+++ b/drivers/gpu/drm/i915_legacy/i915_drv.h
|
|
|
@@ -0,0 +1,3693 @@
|
|
@@ -41810,7 +41810,7 @@ index 000000000000..bf555493e85d
|
|
|
+#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
|
|
|
+#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
|
|
|
+
|
|
|
-+#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
|
|
|
++#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
|
|
|
+#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
|
|
|
+#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
|
|
|
+
|
|
@@ -73683,10 +73683,10 @@ index 000000000000..b5be0abbba35
|
|
|
+}
|
|
|
diff --git a/drivers/gpu/drm/i915_legacy/i915_params.h b/drivers/gpu/drm/i915_legacy/i915_params.h
|
|
|
new file mode 100644
|
|
|
-index 000000000000..8e0d003ff419
|
|
|
+index 000000000000..3f14e9881a0d
|
|
|
--- /dev/null
|
|
|
+++ b/drivers/gpu/drm/i915_legacy/i915_params.h
|
|
|
-@@ -0,0 +1,93 @@
|
|
|
+@@ -0,0 +1,94 @@
|
|
|
+/*
|
|
|
+ * Copyright © 2015 Intel Corporation
|
|
|
+ *
|
|
@@ -73780,6 +73780,7 @@ index 000000000000..8e0d003ff419
|
|
|
+void i915_params_free(struct i915_params *params);
|
|
|
+
|
|
|
+#endif
|
|
|
++
|
|
|
diff --git a/drivers/gpu/drm/i915_legacy/i915_pci.c b/drivers/gpu/drm/i915_legacy/i915_pci.c
|
|
|
new file mode 100644
|
|
|
index 000000000000..f893c2cbce15
|
|
@@ -79847,7 +79848,7 @@ index 000000000000..31dcef181f63
|
|
|
+#endif
|
|
|
diff --git a/drivers/gpu/drm/i915_legacy/i915_reg.h b/drivers/gpu/drm/i915_legacy/i915_reg.h
|
|
|
new file mode 100644
|
|
|
-index 000000000000..eeebefcc34a8
|
|
|
+index 000000000000..cf748b80e640
|
|
|
--- /dev/null
|
|
|
+++ b/drivers/gpu/drm/i915_legacy/i915_reg.h
|
|
|
@@ -0,0 +1,11424 @@
|
|
@@ -87570,7 +87571,7 @@ index 000000000000..eeebefcc34a8
|
|
|
+#define _PIPEC_CHICKEN 0x72038
|
|
|
+#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
|
|
|
+ _PIPEB_CHICKEN)
|
|
|
-+#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
|
|
|
++#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
|
|
|
+#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
|
|
|
+
|
|
|
+/* PCH */
|
|
@@ -138004,7 +138005,7 @@ index 000000000000..2220588e86ac
|
|
|
+#endif
|
|
|
diff --git a/drivers/gpu/drm/i915_legacy/intel_dp.c b/drivers/gpu/drm/i915_legacy/intel_dp.c
|
|
|
new file mode 100644
|
|
|
-index 000000000000..b3b2805014ce
|
|
|
+index 000000000000..560274d1c50b
|
|
|
--- /dev/null
|
|
|
+++ b/drivers/gpu/drm/i915_legacy/intel_dp.c
|
|
|
@@ -0,0 +1,7405 @@
|
|
@@ -140234,10 +140235,10 @@ index 000000000000..b3b2805014ce
|
|
|
+ /*
|
|
|
+ * There are four kinds of DP registers:
|
|
|
+ *
|
|
|
-+ * IBX PCH
|
|
|
-+ * SNB CPU
|
|
|
++ * IBX PCH
|
|
|
++ * SNB CPU
|
|
|
+ * IVB CPU
|
|
|
-+ * CPT PCH
|
|
|
++ * CPT PCH
|
|
|
+ *
|
|
|
+ * IBX PCH and CPU are the same for almost everything,
|
|
|
+ * except that the CPU DP PLL is configured in this
|
|
@@ -140302,7 +140303,7 @@ index 000000000000..b3b2805014ce
|
|
|
+}
|
|
|
+
|
|
|
+#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
|
|
|
-+#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
|
|
|
++#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
|
|
|
+
|
|
|
+#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
|
|
|
+#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
|
|
@@ -218151,7 +218152,7 @@ index 000000000000..0e3bd580e267
|
|
|
+#endif
|
|
|
diff --git a/drivers/gpu/drm/i915_legacy/intel_uncore.c b/drivers/gpu/drm/i915_legacy/intel_uncore.c
|
|
|
new file mode 100644
|
|
|
-index 000000000000..6c9a1e506122
|
|
|
+index 000000000000..d1d51e1121e2
|
|
|
--- /dev/null
|
|
|
+++ b/drivers/gpu/drm/i915_legacy/intel_uncore.c
|
|
|
@@ -0,0 +1,1958 @@
|
|
@@ -220077,7 +220078,7 @@ index 000000000000..6c9a1e506122
|
|
|
+
|
|
|
+/**
|
|
|
+ * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
|
|
|
-+ * a register
|
|
|
++ * a register
|
|
|
+ * @uncore: pointer to struct intel_uncore
|
|
|
+ * @reg: register in question
|
|
|
+ * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
|