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@@ -5186,16 +5186,16 @@ index 000000000000..de5347725564
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+#define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
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+#define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
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+
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-+#define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
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-+#define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
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-+#define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
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-+#define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
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-+#define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
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-+#define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
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-+#define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
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-+#define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
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-+#define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
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-+#define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
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++#define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
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++#define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
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++#define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
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++#define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
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++#define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
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++#define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
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++#define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
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++#define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
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++#define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
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++#define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
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+#define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
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+
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+#define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
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@@ -41810,7 +41810,7 @@ index 000000000000..066fd2a12851
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+#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
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+#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
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+
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-+#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
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++#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
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+#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
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+#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
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+
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@@ -73686,7 +73686,7 @@ new file mode 100644
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index 000000000000..3f14e9881a0d
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--- /dev/null
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+++ b/drivers/gpu/drm/i915_legacy/i915_params.h
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-@@ -0,0 +1,94 @@
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+@@ -0,0 +1,93 @@
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+/*
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+ * Copyright © 2015 Intel Corporation
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+ *
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@@ -73780,7 +73780,6 @@ index 000000000000..3f14e9881a0d
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+void i915_params_free(struct i915_params *params);
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+
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+#endif
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-+
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diff --git a/drivers/gpu/drm/i915_legacy/i915_pci.c b/drivers/gpu/drm/i915_legacy/i915_pci.c
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new file mode 100644
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index 000000000000..f893c2cbce15
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@@ -87571,7 +87570,7 @@ index 000000000000..cf748b80e640
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+#define _PIPEC_CHICKEN 0x72038
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+#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
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+ _PIPEB_CHICKEN)
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-+#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
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++#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
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+#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
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+
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+/* PCH */
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@@ -140235,10 +140234,10 @@ index 000000000000..560274d1c50b
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+ /*
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+ * There are four kinds of DP registers:
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+ *
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-+ * IBX PCH
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-+ * SNB CPU
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++ * IBX PCH
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++ * SNB CPU
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+ * IVB CPU
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-+ * CPT PCH
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++ * CPT PCH
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+ *
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+ * IBX PCH and CPU are the same for almost everything,
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+ * except that the CPU DP PLL is configured in this
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@@ -140303,7 +140302,7 @@ index 000000000000..560274d1c50b
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+}
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+
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+#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
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-+#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
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++#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
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+
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+#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
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+#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
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@@ -220078,7 +220077,7 @@ index 000000000000..d1d51e1121e2
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+
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+/**
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+ * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
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-+ * a register
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++ * a register
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+ * @uncore: pointer to struct intel_uncore
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+ * @reg: register in question
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+ * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
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qzed