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9e66eb160c
Also, the enable() function is now correct and will use the right registers and values. In addition to that, write_register() and read_registers() are not relying on identity mapping anymore.
232 lines
7.5 KiB
C++
232 lines
7.5 KiB
C++
/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <AK/Assertions.h>
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#include <AK/Types.h>
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/Interrupts/APIC.h>
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#include <Kernel/VM/MemoryManager.h>
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#include <LibBareMetal/IO.h>
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#define IRQ_APIC_SPURIOUS 0x1f
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#define APIC_BASE_MSR 0x1b
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#define APIC_REG_EOI 0xb0
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#define APIC_REG_LD 0xd0
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#define APIC_REG_DF 0xe0
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#define APIC_REG_SIV 0xf0
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#define APIC_REG_ICR_LOW 0x300
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#define APIC_REG_ICR_HIGH 0x310
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#define APIC_REG_LVT_TIMER 0x320
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#define APIC_REG_LVT_THERMAL 0x330
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#define APIC_REG_LVT_PERFORMANCE_COUNTER 0x340
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#define APIC_REG_LVT_LINT0 0x350
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#define APIC_REG_LVT_LINT1 0x360
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#define APIC_REG_LVT_ERR 0x370
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namespace Kernel {
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extern "C" void apic_spurious_interrupt_entry();
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asm(
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".globl apic_spurious_interrupt_entry \n"
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"apic_spurious_interrupt_entry: \n"
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" iret\n");
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namespace APIC {
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class ICRReg {
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u32 m_reg { 0 };
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public:
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enum DeliveryMode {
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Fixed = 0x0,
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LowPriority = 0x1,
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SMI = 0x2,
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NMI = 0x4,
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INIT = 0x5,
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StartUp = 0x6,
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};
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enum DestinationMode {
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Physical = 0x0,
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Logical = 0x0,
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};
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enum Level {
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DeAssert = 0x0,
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Assert = 0x1
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};
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enum class TriggerMode {
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Edge = 0x0,
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Level = 0x1,
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};
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enum DestinationShorthand {
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NoShorthand = 0x0,
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Self = 0x1,
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AllIncludingSelf = 0x2,
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AllExcludingSelf = 0x3,
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};
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ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination)
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: m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
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{
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}
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u32 low() const { return m_reg; }
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u32 high() const { return 0; }
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};
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static volatile u8* g_apic_base = nullptr;
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static PhysicalAddress get_base()
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{
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u32 lo, hi;
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MSR msr(APIC_BASE_MSR);
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msr.get(lo, hi);
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return PhysicalAddress(lo & 0xfffff000);
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}
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static void set_base(const PhysicalAddress& base)
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{
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u32 hi = 0;
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u32 lo = base.get() | 0x800;
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MSR msr(APIC_BASE_MSR);
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msr.set(lo, hi);
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}
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static void write_register(u32 offset, u32 value)
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{
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auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Write Access", Region::Access::Read | Region::Access::Write, false, true);
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auto* lapic = (u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
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*lapic = value;
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}
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static u32 read_register(u32 offset)
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{
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auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Read Access", Region::Access::Read, false, true);
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auto* lapic = (u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
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return *lapic;
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}
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static void write_icr(const ICRReg& icr)
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{
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write_register(APIC_REG_ICR_HIGH, icr.high());
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write_register(APIC_REG_ICR_LOW, icr.low());
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}
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#define APIC_LVT_MASKED (1 << 16)
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#define APIC_LVT_TRIGGER_LEVEL (1 << 14)
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#define APIC_LVT(iv, dm) ((iv & 0xff) | ((dm & 0x7) << 8))
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asm(
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".globl apic_ap_start \n"
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".type apic_ap_start, @function \n"
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"apic_ap_start: \n"
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".set begin_apic_ap_start, . \n"
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" jmp apic_ap_start\n" // TODO: implement
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".set end_apic_ap_start, . \n"
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"\n"
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".globl apic_ap_start_size \n"
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"apic_ap_start_size: \n"
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".word end_apic_ap_start - begin_apic_ap_start \n");
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extern "C" void apic_ap_start(void);
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extern "C" u16 apic_ap_start_size;
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void eoi()
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{
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write_register(APIC_REG_EOI, 0x0);
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}
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bool init()
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{
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if (!MSR::have())
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return false;
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// check if we support local apic
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CPUID id(1);
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if ((id.edx() & (1 << 9)) == 0)
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return false;
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PhysicalAddress apic_base = get_base();
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kprintf("Initializing APIC, base: P%x\n", apic_base);
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set_base(apic_base);
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g_apic_base = apic_base.as_ptr();
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return true;
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}
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void enable_bsp()
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{
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// FIXME: Ensure this method can only be executed by the BSP.
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enable(0);
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}
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void enable(u32 cpu)
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{
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kprintf("Enabling local APIC for cpu #%u\n", cpu);
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// set spurious interrupt vector
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write_register(APIC_REG_SIV, read_register(APIC_REG_SIV) | 0x100);
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// local destination mode (flat mode)
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write_register(APIC_REG_DF, 0xf0000000);
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// set destination id (note that this limits it to 8 cpus)
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write_register(APIC_REG_LD, (1 << cpu) << 24);
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register_interrupt_handler(IRQ_APIC_SPURIOUS, apic_spurious_interrupt_entry);
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write_register(APIC_REG_LVT_TIMER, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_THERMAL, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_PERFORMANCE_COUNTER, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_LINT0, APIC_LVT(0x1f, 7) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_LINT1, APIC_LVT(0xff, 4) | APIC_LVT_TRIGGER_LEVEL); // nmi
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write_register(APIC_REG_LVT_ERR, APIC_LVT(0xe3, 0) | APIC_LVT_MASKED);
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if (cpu != 0) {
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static volatile u32 foo = 0;
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// INIT
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write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
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for (foo = 0; foo < 0x800000; foo++)
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; // TODO: 10 millisecond delay
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for (int i = 0; i < 2; i++) {
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// SIPI
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write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
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for (foo = 0; foo < 0x80000; foo++)
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; // TODO: 200 microsecond delay
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}
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}
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}
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}
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}
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