ddc5c41253
Thanks to Andrew Kaster, which gave a review back in October, about a big PR I opened (#15502), I managed to figure out why we always had a problem with the first byte being read into the EDID buffer with the GMBus code. It turns out that this simple invalid cast was making the entire problem and using the correct AK::Array::data() method fixed this notorious long standing problem for good.
707 lines
27 KiB
C++
707 lines
27 KiB
C++
/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Debug.h>
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#include <Kernel/Devices/DeviceManagement.h>
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#include <Kernel/Graphics/Console/ContiguousFramebufferConsole.h>
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#include <Kernel/Graphics/GraphicsManagement.h>
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#include <Kernel/Graphics/Intel/NativeDisplayConnector.h>
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#include <Kernel/Memory/Region.h>
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namespace Kernel {
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namespace IntelGraphics {
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#define DDC2_I2C_ADDRESS 0x50
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struct PLLSettings {
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bool is_valid() const { return (n != 0 && m1 != 0 && m2 != 0 && p1 != 0 && p2 != 0); }
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u64 compute_dot_clock(u64 refclock) const
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{
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return (refclock * (5 * m1 + m2) / n) / (p1 * p2);
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}
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u64 compute_vco(u64 refclock) const
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{
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return refclock * (5 * m1 + m2) / n;
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}
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u64 compute_m() const
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{
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return 5 * m1 + m2;
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}
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u64 compute_p() const
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{
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return p1 * p2;
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}
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u64 n { 0 };
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u64 m1 { 0 };
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u64 m2 { 0 };
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u64 p1 { 0 };
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u64 p2 { 0 };
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};
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static constexpr PLLMaxSettings G35Limits {
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{ 20'000'000, 400'000'000 }, // values in Hz, dot_clock
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{ 1'400'000'000, 2'800'000'000 }, // values in Hz, VCO
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{ 3, 8 }, // n
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{ 70, 120 }, // m
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{ 10, 20 }, // m1
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{ 5, 9 }, // m2
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{ 5, 80 }, // p
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{ 1, 8 }, // p1
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{ 5, 10 } // p2
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};
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}
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static Graphics::Modesetting calculate_modesetting_from_edid(EDID::Parser& edid, size_t index)
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{
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auto details = edid.detailed_timing(index).release_value();
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Graphics::Modesetting mode;
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VERIFY(details.pixel_clock_khz());
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mode.pixel_clock_in_khz = details.pixel_clock_khz();
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size_t horizontal_active = details.horizontal_addressable_pixels();
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size_t horizontal_sync_offset = details.horizontal_front_porch_pixels();
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mode.horizontal.active = horizontal_active;
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mode.horizontal.sync_start = horizontal_active + horizontal_sync_offset;
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mode.horizontal.sync_end = horizontal_active + horizontal_sync_offset + details.horizontal_sync_pulse_width_pixels();
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mode.horizontal.total = horizontal_active + details.horizontal_blanking_pixels();
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size_t vertical_active = details.vertical_addressable_lines();
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size_t vertical_sync_offset = details.vertical_front_porch_lines();
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mode.vertical.active = vertical_active;
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mode.vertical.sync_start = vertical_active + vertical_sync_offset;
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mode.vertical.sync_end = vertical_active + vertical_sync_offset + details.vertical_sync_pulse_width_lines();
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mode.vertical.total = vertical_active + details.vertical_blanking_lines();
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return mode;
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}
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static bool check_pll_settings(IntelGraphics::PLLSettings const& settings, size_t reference_clock, IntelGraphics::PLLMaxSettings const& limits)
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{
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if (settings.n < limits.n.min || settings.n > limits.n.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "N is invalid {}", settings.n);
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return false;
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}
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if (settings.m1 < limits.m1.min || settings.m1 > limits.m1.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m1 is invalid {}", settings.m1);
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return false;
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}
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if (settings.m2 < limits.m2.min || settings.m2 > limits.m2.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m2 is invalid {}", settings.m2);
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return false;
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}
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if (settings.p1 < limits.p1.min || settings.p1 > limits.p1.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "p1 is invalid {}", settings.p1);
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return false;
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}
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if (settings.m1 <= settings.m2) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m2 is invalid {} as it is bigger than m1 {}", settings.m2, settings.m1);
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return false;
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}
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auto m = settings.compute_m();
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auto p = settings.compute_p();
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if (m < limits.m.min || m > limits.m.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m invalid {}", m);
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return false;
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}
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if (p < limits.p.min || p > limits.p.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "p invalid {}", p);
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return false;
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}
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auto dot = settings.compute_dot_clock(reference_clock);
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auto vco = settings.compute_vco(reference_clock);
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if (dot < limits.dot_clock.min || dot > limits.dot_clock.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Dot clock invalid {}", dot);
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return false;
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}
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if (vco < limits.vco.min || vco > limits.vco.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "VCO clock invalid {}", vco);
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return false;
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}
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return true;
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}
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static size_t find_absolute_difference(u64 target_frequency, u64 checked_frequency)
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{
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if (target_frequency >= checked_frequency)
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return target_frequency - checked_frequency;
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return checked_frequency - target_frequency;
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}
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Optional<IntelGraphics::PLLSettings> IntelNativeDisplayConnector::create_pll_settings(u64 target_frequency, u64 reference_clock, IntelGraphics::PLLMaxSettings const& limits)
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{
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IntelGraphics::PLLSettings settings;
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IntelGraphics::PLLSettings best_settings;
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// FIXME: Is this correct for all Intel Native graphics cards?
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settings.p2 = 10;
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Check PLL settings for ref clock of {} Hz, for target of {} Hz", reference_clock, target_frequency);
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u64 best_difference = 0xffffffff;
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for (settings.n = limits.n.min; settings.n <= limits.n.max; ++settings.n) {
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for (settings.m1 = limits.m1.max; settings.m1 >= limits.m1.min; --settings.m1) {
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for (settings.m2 = limits.m2.max; settings.m2 >= limits.m2.min; --settings.m2) {
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for (settings.p1 = limits.p1.max; settings.p1 >= limits.p1.min; --settings.p1) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Check PLL settings for {} {} {} {} {}", settings.n, settings.m1, settings.m2, settings.p1, settings.p2);
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if (!check_pll_settings(settings, reference_clock, limits))
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continue;
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auto current_dot_clock = settings.compute_dot_clock(reference_clock);
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if (current_dot_clock == target_frequency)
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return settings;
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auto difference = find_absolute_difference(target_frequency, current_dot_clock);
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if (difference < best_difference && (current_dot_clock > target_frequency)) {
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best_settings = settings;
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best_difference = difference;
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}
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}
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}
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}
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}
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if (best_settings.is_valid())
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return best_settings;
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return {};
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}
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ErrorOr<NonnullLockRefPtr<IntelNativeDisplayConnector>> IntelNativeDisplayConnector::try_create(PhysicalAddress framebuffer_address, size_t framebuffer_resource_size, PhysicalAddress registers_region_address, size_t registers_region_length)
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{
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auto registers_region = TRY(MM.allocate_kernel_region(PhysicalAddress(registers_region_address), registers_region_length, "Intel Native Graphics Registers"sv, Memory::Region::Access::ReadWrite));
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auto connector = TRY(DeviceManagement::try_create_device<IntelNativeDisplayConnector>(framebuffer_address, framebuffer_resource_size, move(registers_region)));
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TRY(connector->initialize_gmbus_settings_and_read_edid());
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// Note: This is very important to set the resolution to something safe so we
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// can create a framebuffer console with valid resolution.
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{
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SpinlockLocker control_lock(connector->m_control_lock);
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TRY(connector->set_safe_mode_setting());
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}
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TRY(connector->create_attached_framebuffer_console());
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return connector;
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}
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ErrorOr<void> IntelNativeDisplayConnector::initialize_gmbus_settings_and_read_edid()
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{
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gmbus_read_edid();
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return {};
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}
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ErrorOr<void> IntelNativeDisplayConnector::set_y_offset(size_t)
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{
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return Error::from_errno(ENOTIMPL);
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}
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ErrorOr<void> IntelNativeDisplayConnector::unblank()
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{
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return Error::from_errno(ENOTIMPL);
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}
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void IntelNativeDisplayConnector::enable_console()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_framebuffer_console);
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m_framebuffer_console->enable();
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}
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void IntelNativeDisplayConnector::disable_console()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_framebuffer_console);
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m_framebuffer_console->disable();
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}
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ErrorOr<void> IntelNativeDisplayConnector::flush_first_surface()
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{
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return Error::from_errno(ENOTSUP);
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}
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ErrorOr<void> IntelNativeDisplayConnector::create_attached_framebuffer_console()
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{
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m_framebuffer_console = Graphics::ContiguousFramebufferConsole::initialize(m_framebuffer_address.value(), m_current_mode_setting.horizontal_active, m_current_mode_setting.vertical_active, m_current_mode_setting.horizontal_stride);
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GraphicsManagement::the().set_console(*m_framebuffer_console);
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return {};
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}
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IntelNativeDisplayConnector::IntelNativeDisplayConnector(PhysicalAddress framebuffer_address, size_t framebuffer_resource_size, NonnullOwnPtr<Memory::Region> registers_region)
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: DisplayConnector(framebuffer_address, framebuffer_resource_size, true)
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, m_registers_region(move(registers_region))
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{
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{
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SpinlockLocker control_lock(m_control_lock);
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set_gmbus_default_rate();
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set_gmbus_pin_pair(IntelGraphics::GMBusPinPair::DedicatedAnalog);
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}
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}
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ErrorOr<void> IntelNativeDisplayConnector::set_mode_setting(DisplayConnector::ModeSetting const&)
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{
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return Error::from_errno(ENOTIMPL);
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}
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ErrorOr<void> IntelNativeDisplayConnector::set_safe_mode_setting()
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{
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set_safe_crt_resolution();
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return {};
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}
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void IntelNativeDisplayConnector::enable_vga_plane()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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}
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[[maybe_unused]] static StringView convert_register_index_to_string(IntelGraphics::RegisterIndex index)
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{
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switch (index) {
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case IntelGraphics::RegisterIndex::PipeAConf:
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return "PipeAConf"sv;
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case IntelGraphics::RegisterIndex::PipeBConf:
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return "PipeBConf"sv;
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case IntelGraphics::RegisterIndex::GMBusData:
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return "GMBusData"sv;
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case IntelGraphics::RegisterIndex::GMBusStatus:
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return "GMBusStatus"sv;
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case IntelGraphics::RegisterIndex::GMBusCommand:
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return "GMBusCommand"sv;
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case IntelGraphics::RegisterIndex::GMBusClock:
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return "GMBusClock"sv;
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case IntelGraphics::RegisterIndex::DisplayPlaneAControl:
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return "DisplayPlaneAControl"sv;
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case IntelGraphics::RegisterIndex::DisplayPlaneALinearOffset:
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return "DisplayPlaneALinearOffset"sv;
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case IntelGraphics::RegisterIndex::DisplayPlaneAStride:
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return "DisplayPlaneAStride"sv;
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case IntelGraphics::RegisterIndex::DisplayPlaneASurface:
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return "DisplayPlaneASurface"sv;
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case IntelGraphics::RegisterIndex::DPLLDivisorA0:
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return "DPLLDivisorA0"sv;
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case IntelGraphics::RegisterIndex::DPLLDivisorA1:
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return "DPLLDivisorA1"sv;
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case IntelGraphics::RegisterIndex::DPLLControlA:
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return "DPLLControlA"sv;
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case IntelGraphics::RegisterIndex::DPLLControlB:
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return "DPLLControlB"sv;
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case IntelGraphics::RegisterIndex::DPLLMultiplierA:
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return "DPLLMultiplierA"sv;
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case IntelGraphics::RegisterIndex::HTotalA:
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return "HTotalA"sv;
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case IntelGraphics::RegisterIndex::HBlankA:
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return "HBlankA"sv;
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case IntelGraphics::RegisterIndex::HSyncA:
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return "HSyncA"sv;
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case IntelGraphics::RegisterIndex::VTotalA:
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return "VTotalA"sv;
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case IntelGraphics::RegisterIndex::VBlankA:
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return "VBlankA"sv;
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case IntelGraphics::RegisterIndex::VSyncA:
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return "VSyncA"sv;
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case IntelGraphics::RegisterIndex::PipeASource:
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return "PipeASource"sv;
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case IntelGraphics::RegisterIndex::AnalogDisplayPort:
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return "AnalogDisplayPort"sv;
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case IntelGraphics::RegisterIndex::VGADisplayPlaneControl:
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return "VGADisplayPlaneControl"sv;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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void IntelNativeDisplayConnector::write_to_register(IntelGraphics::RegisterIndex index, u32 value) const
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{
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VERIFY(m_control_lock.is_locked());
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SpinlockLocker lock(m_registers_lock);
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel Graphics Display Connector:: Write to {} value of {:x}", convert_register_index_to_string(index), value);
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auto* reg = (u32 volatile*)m_registers_region->vaddr().offset(to_underlying(index)).as_ptr();
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*reg = value;
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}
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u32 IntelNativeDisplayConnector::read_from_register(IntelGraphics::RegisterIndex index) const
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{
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VERIFY(m_control_lock.is_locked());
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SpinlockLocker lock(m_registers_lock);
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auto* reg = (u32 volatile*)m_registers_region->vaddr().offset(to_underlying(index)).as_ptr();
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u32 value = *reg;
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel Graphics Display Connector: Read from {} value of {:x}", convert_register_index_to_string(index), value);
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return value;
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}
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bool IntelNativeDisplayConnector::pipe_a_enabled() const
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{
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VERIFY(m_control_lock.is_locked());
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return read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 30);
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}
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bool IntelNativeDisplayConnector::pipe_b_enabled() const
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{
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VERIFY(m_control_lock.is_locked());
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return read_from_register(IntelGraphics::RegisterIndex::PipeBConf) & (1 << 30);
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}
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bool IntelNativeDisplayConnector::gmbus_wait_for(IntelGraphics::GMBusStatus desired_status, Optional<size_t> milliseconds_timeout)
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{
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VERIFY(m_control_lock.is_locked());
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size_t milliseconds_passed = 0;
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while (1) {
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if (milliseconds_timeout.has_value() && milliseconds_timeout.value() < milliseconds_passed)
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return false;
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full_memory_barrier();
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u32 status = read_from_register(IntelGraphics::RegisterIndex::GMBusStatus);
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full_memory_barrier();
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VERIFY(!(status & (1 << 10))); // error happened
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switch (desired_status) {
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case IntelGraphics::GMBusStatus::HardwareReady:
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if (status & (1 << 11))
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return true;
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break;
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case IntelGraphics::GMBusStatus::TransactionCompletion:
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if (status & (1 << 14))
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return true;
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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microseconds_delay(1000);
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milliseconds_passed++;
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}
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}
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void IntelNativeDisplayConnector::gmbus_write(unsigned address, u32 byte)
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(address < 256);
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full_memory_barrier();
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write_to_register(IntelGraphics::RegisterIndex::GMBusData, byte);
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full_memory_barrier();
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write_to_register(IntelGraphics::RegisterIndex::GMBusCommand, ((address << 1) | (1 << 16) | (IntelGraphics::GMBusCycle::Wait << 25) | (1 << 30)));
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full_memory_barrier();
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gmbus_wait_for(IntelGraphics::GMBusStatus::TransactionCompletion, {});
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}
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void IntelNativeDisplayConnector::gmbus_read(unsigned address, u8* buf, size_t length)
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{
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VERIFY(address < 256);
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VERIFY(m_control_lock.is_locked());
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size_t nread = 0;
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auto read_set = [&] {
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full_memory_barrier();
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u32 data = read_from_register(IntelGraphics::RegisterIndex::GMBusData);
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full_memory_barrier();
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for (size_t index = 0; index < 4; index++) {
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if (nread == length)
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break;
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buf[nread] = (data >> (8 * index)) & 0xFF;
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nread++;
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}
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};
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full_memory_barrier();
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write_to_register(IntelGraphics::RegisterIndex::GMBusCommand, (1 | (address << 1) | (length << 16) | (IntelGraphics::GMBusCycle::Wait << 25) | (1 << 30)));
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full_memory_barrier();
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while (nread < length) {
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gmbus_wait_for(IntelGraphics::GMBusStatus::HardwareReady, {});
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read_set();
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}
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gmbus_wait_for(IntelGraphics::GMBusStatus::TransactionCompletion, {});
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}
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void IntelNativeDisplayConnector::gmbus_read_edid()
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{
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Array<u8, 128> crt_edid_bytes {};
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{
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SpinlockLocker control_lock(m_control_lock);
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gmbus_write(DDC2_I2C_ADDRESS, 0);
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gmbus_read(DDC2_I2C_ADDRESS, crt_edid_bytes.data(), crt_edid_bytes.size());
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}
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set_edid_bytes(crt_edid_bytes);
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}
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bool IntelNativeDisplayConnector::is_resolution_valid(size_t, size_t)
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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// FIXME: Check that we are able to modeset to the requested resolution!
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return true;
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}
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void IntelNativeDisplayConnector::disable_output()
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{
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VERIFY(m_control_lock.is_locked());
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disable_dac_output();
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disable_all_planes();
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disable_pipe_a();
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disable_pipe_b();
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disable_dpll();
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disable_vga_emulation();
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}
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void IntelNativeDisplayConnector::enable_output(PhysicalAddress fb_address, size_t width)
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(!pipe_a_enabled());
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enable_pipe_a();
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enable_primary_plane(fb_address, width);
|
|
enable_dac_output();
|
|
}
|
|
|
|
static size_t compute_dac_multiplier(size_t pixel_clock_in_khz)
|
|
{
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel native graphics: Pixel clock is {} KHz", pixel_clock_in_khz);
|
|
VERIFY(pixel_clock_in_khz >= 25000);
|
|
if (pixel_clock_in_khz >= 100000) {
|
|
return 1;
|
|
} else if (pixel_clock_in_khz >= 50000) {
|
|
return 2;
|
|
} else {
|
|
return 4;
|
|
}
|
|
}
|
|
|
|
bool IntelNativeDisplayConnector::set_safe_crt_resolution()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
SpinlockLocker modeset_lock(m_modeset_lock);
|
|
|
|
// Note: Just in case we still allow access to VGA IO ports, disable it now.
|
|
GraphicsManagement::the().disable_vga_emulation_access_permanently();
|
|
|
|
// FIXME: Get the requested resolution from the EDID!!
|
|
auto modesetting = calculate_modesetting_from_edid(m_edid_parser.value(), 0);
|
|
|
|
disable_output();
|
|
|
|
auto dac_multiplier = compute_dac_multiplier(modesetting.pixel_clock_in_khz);
|
|
auto pll_settings = create_pll_settings((1000 * modesetting.pixel_clock_in_khz * dac_multiplier), 96'000'000, IntelGraphics::G35Limits);
|
|
if (!pll_settings.has_value())
|
|
VERIFY_NOT_REACHED();
|
|
auto settings = pll_settings.value();
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "PLL settings for {} {} {} {} {}", settings.n, settings.m1, settings.m2, settings.p1, settings.p2);
|
|
enable_dpll_without_vga(pll_settings.value(), dac_multiplier);
|
|
set_display_timings(modesetting);
|
|
enable_output(m_framebuffer_address.value(), modesetting.horizontal.blanking_start());
|
|
|
|
DisplayConnector::ModeSetting mode_set {
|
|
.horizontal_stride = modesetting.horizontal.blanking_start() * sizeof(u32),
|
|
.pixel_clock_in_khz = 0,
|
|
.horizontal_active = modesetting.horizontal.blanking_start(),
|
|
.horizontal_front_porch_pixels = 0,
|
|
.horizontal_sync_time_pixels = 0,
|
|
.horizontal_blank_pixels = 0,
|
|
.vertical_active = modesetting.vertical.blanking_start(),
|
|
.vertical_front_porch_lines = 0,
|
|
.vertical_sync_time_lines = 0,
|
|
.vertical_blank_lines = 0,
|
|
.horizontal_offset = 0,
|
|
.vertical_offset = 0,
|
|
};
|
|
|
|
m_current_mode_setting = mode_set;
|
|
|
|
if (m_framebuffer_console)
|
|
m_framebuffer_console->set_resolution(m_current_mode_setting.horizontal_active, m_current_mode_setting.vertical_active, m_current_mode_setting.horizontal_stride);
|
|
|
|
return true;
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::set_display_timings(Graphics::Modesetting const& modesetting)
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
VERIFY(!(read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 31)));
|
|
VERIFY(!(read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 30)));
|
|
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "htotal - {}, {}", (modesetting.horizontal.active - 1), (modesetting.horizontal.total - 1));
|
|
write_to_register(IntelGraphics::RegisterIndex::HTotalA, (modesetting.horizontal.active - 1) | (modesetting.horizontal.total - 1) << 16);
|
|
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "hblank - {}, {}", (modesetting.horizontal.blanking_start() - 1), (modesetting.horizontal.blanking_end() - 1));
|
|
write_to_register(IntelGraphics::RegisterIndex::HBlankA, (modesetting.horizontal.blanking_start() - 1) | (modesetting.horizontal.blanking_end() - 1) << 16);
|
|
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "hsync - {}, {}", (modesetting.horizontal.sync_start - 1), (modesetting.horizontal.sync_end - 1));
|
|
write_to_register(IntelGraphics::RegisterIndex::HSyncA, (modesetting.horizontal.sync_start - 1) | (modesetting.horizontal.sync_end - 1) << 16);
|
|
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "vtotal - {}, {}", (modesetting.vertical.active - 1), (modesetting.vertical.total - 1));
|
|
write_to_register(IntelGraphics::RegisterIndex::VTotalA, (modesetting.vertical.active - 1) | (modesetting.vertical.total - 1) << 16);
|
|
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "vblank - {}, {}", (modesetting.vertical.blanking_start() - 1), (modesetting.vertical.blanking_end() - 1));
|
|
write_to_register(IntelGraphics::RegisterIndex::VBlankA, (modesetting.vertical.blanking_start() - 1) | (modesetting.vertical.blanking_end() - 1) << 16);
|
|
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "vsync - {}, {}", (modesetting.vertical.sync_start - 1), (modesetting.vertical.sync_end - 1));
|
|
write_to_register(IntelGraphics::RegisterIndex::VSyncA, (modesetting.vertical.sync_start - 1) | (modesetting.vertical.sync_end - 1) << 16);
|
|
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "sourceSize - {}, {}", (modesetting.vertical.active - 1), (modesetting.horizontal.active - 1));
|
|
write_to_register(IntelGraphics::RegisterIndex::PipeASource, (modesetting.vertical.active - 1) | (modesetting.horizontal.active - 1) << 16);
|
|
|
|
microseconds_delay(200);
|
|
}
|
|
|
|
bool IntelNativeDisplayConnector::wait_for_enabled_pipe_a(size_t milliseconds_timeout) const
|
|
{
|
|
size_t current_time = 0;
|
|
while (current_time < milliseconds_timeout) {
|
|
if (pipe_a_enabled())
|
|
return true;
|
|
microseconds_delay(1000);
|
|
current_time++;
|
|
}
|
|
return false;
|
|
}
|
|
bool IntelNativeDisplayConnector::wait_for_disabled_pipe_a(size_t milliseconds_timeout) const
|
|
{
|
|
size_t current_time = 0;
|
|
while (current_time < milliseconds_timeout) {
|
|
if (!pipe_a_enabled())
|
|
return true;
|
|
microseconds_delay(1000);
|
|
current_time++;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool IntelNativeDisplayConnector::wait_for_disabled_pipe_b(size_t milliseconds_timeout) const
|
|
{
|
|
size_t current_time = 0;
|
|
while (current_time < milliseconds_timeout) {
|
|
if (!pipe_b_enabled())
|
|
return true;
|
|
microseconds_delay(1000);
|
|
current_time++;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::disable_dpll()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::DPLLControlA, 0);
|
|
write_to_register(IntelGraphics::RegisterIndex::DPLLControlB, 0);
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::disable_pipe_a()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::PipeAConf, 0);
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe A");
|
|
wait_for_disabled_pipe_a(100);
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe A - done.");
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::disable_pipe_b()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::PipeAConf, 0);
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe B");
|
|
wait_for_disabled_pipe_b(100);
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe B - done.");
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::set_gmbus_default_rate()
|
|
{
|
|
// FIXME: Verify GMBUS Rate Select is set only when GMBUS is idle
|
|
VERIFY(m_control_lock.is_locked());
|
|
// Set the rate to 100KHz
|
|
write_to_register(IntelGraphics::RegisterIndex::GMBusClock, read_from_register(IntelGraphics::RegisterIndex::GMBusClock) & ~(0b111 << 8));
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::enable_pipe_a()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
VERIFY(!(read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 31)));
|
|
VERIFY(!(read_from_register(IntelGraphics::RegisterIndex::PipeAConf) & (1 << 30)));
|
|
write_to_register(IntelGraphics::RegisterIndex::PipeAConf, (1 << 31) | (1 << 24));
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "enabling Pipe A");
|
|
// FIXME: Seems like my video card is buggy and doesn't set the enabled bit (bit 30)!!
|
|
wait_for_enabled_pipe_a(100);
|
|
dbgln_if(INTEL_GRAPHICS_DEBUG, "enabling Pipe A - done.");
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::enable_primary_plane(PhysicalAddress fb_address, size_t width)
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
VERIFY(((width * 4) % 64 == 0));
|
|
|
|
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneAStride, width * 4);
|
|
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneALinearOffset, 0);
|
|
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneASurface, fb_address.get());
|
|
|
|
// FIXME: Serenity uses BGR 32 bit pixel format, but maybe we should try to determine it somehow!
|
|
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneAControl, (0b0110 << 26) | (1 << 31));
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::set_dpll_registers(IntelGraphics::PLLSettings const& settings)
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::DPLLDivisorA0, (settings.m2 - 2) | ((settings.m1 - 2) << 8) | ((settings.n - 2) << 16));
|
|
write_to_register(IntelGraphics::RegisterIndex::DPLLDivisorA1, (settings.m2 - 2) | ((settings.m1 - 2) << 8) | ((settings.n - 2) << 16));
|
|
|
|
write_to_register(IntelGraphics::RegisterIndex::DPLLControlA, 0);
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::enable_dpll_without_vga(IntelGraphics::PLLSettings const& settings, size_t dac_multiplier)
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
|
|
set_dpll_registers(settings);
|
|
|
|
microseconds_delay(200);
|
|
|
|
write_to_register(IntelGraphics::RegisterIndex::DPLLControlA, (6 << 9) | (settings.p1) << 16 | (1 << 26) | (1 << 28) | (1 << 31));
|
|
write_to_register(IntelGraphics::RegisterIndex::DPLLMultiplierA, (dac_multiplier - 1) | ((dac_multiplier - 1) << 8));
|
|
|
|
// The specification says we should wait (at least) about 150 microseconds
|
|
// after enabling the DPLL to allow the clock to stabilize
|
|
microseconds_delay(200);
|
|
VERIFY(read_from_register(IntelGraphics::RegisterIndex::DPLLControlA) & (1 << 31));
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::set_gmbus_pin_pair(IntelGraphics::GMBusPinPair pin_pair)
|
|
{
|
|
// FIXME: Verify GMBUS is idle
|
|
VERIFY(m_control_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::GMBusClock, (read_from_register(IntelGraphics::RegisterIndex::GMBusClock) & (~0b111)) | (pin_pair & 0b111));
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::disable_dac_output()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::AnalogDisplayPort, 0b11 << 10);
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::enable_dac_output()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::AnalogDisplayPort, (1 << 31));
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::disable_vga_emulation()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::VGADisplayPlaneControl, (1 << 31));
|
|
read_from_register(IntelGraphics::RegisterIndex::VGADisplayPlaneControl);
|
|
}
|
|
|
|
void IntelNativeDisplayConnector::disable_all_planes()
|
|
{
|
|
VERIFY(m_control_lock.is_locked());
|
|
VERIFY(m_modeset_lock.is_locked());
|
|
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneAControl, 0);
|
|
write_to_register(IntelGraphics::RegisterIndex::DisplayPlaneBControl, 0);
|
|
}
|
|
|
|
}
|