2def16a3d2
In the real world, graphics hardware tend to have multiple display connectors. However, usually the connectors share one register space but still keeping different PLL timings and display lanes. This new class should represent a group of multiple display connectors working together in the same Intel graphics adapter. This opens an opportunity to abstract the interface so we could support future Intel iGPU generations. This is also a preparation before the driver can support newer devices and utilize their capabilities. The mentioned preparation is applied in a these aspects: 1. The code is splitted into more classes to adjust to future expansion. 2 classes are introduced: IntelDisplayPlane and IntelDisplayTranscoder, so the IntelDisplayPlane controls the plane registers and second class controls the pipeline (transcoder, encoder) registers. On gen4 it's not really useful because there are probably one plane and one encoder to care about, but in future generations, there are likely to be multiple transcoders and planes to accommodate multi head support. 2. The set_edid_bytes method in the DisplayConnector class can now be told to not assume the provided EDID bytes are always invalid. Therefore it can refrain from printing error messages if this flag parameter is true. This is useful for supporting real hardware situation when on boot not all ports are connected to a monitor, which can result in floating bus condition (essentially all the bytes we read are 0xFF). 3. An IntelNativeDisplayConnector could now be set to flag other types of connections such as eDP (embedded DisplayPort), Analog output, etc. This is important because on the Intel gen4 graphics we could assume to have one analog output connector, but on future generations this is very likely to not be the case, as there might be no VGA outputs, but rather only an eDP connector which is converted to VGA by a design choice of the motherboard manufacturer. 4. Add ConnectorIndex to IntelNativeDisplayConnector class - Currently this is used to verify we always handle the correct connector when doing modesetting. Later, it will be used to locate special settings needed when handling connector requests. 5. Prepare to support more types of display planes. For example, the Intel Skylake register set for display planes is a bit different, so let's ensure we can properly support it in the near future.
91 lines
2.6 KiB
C++
91 lines
2.6 KiB
C++
/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/RefPtr.h>
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#include <AK/Try.h>
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#include <AK/Types.h>
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#include <Kernel/Graphics/DisplayConnector.h>
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#include <Kernel/Graphics/Intel/Definitions.h>
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#include <Kernel/Locking/Spinlock.h>
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#include <Kernel/Memory/TypedMapping.h>
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namespace Kernel {
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class IntelDisplayConnectorGroup;
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class IntelDisplayTranscoder {
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public:
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// Note: This is used to "cache" all the registers we wrote to, because
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// we might not be able to read them directly from hardware later.
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struct ShadowRegisters {
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u32 horizontal_total;
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u32 horizontal_blank;
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u32 horizontal_sync;
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u32 vertical_total;
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u32 vertical_blank;
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u32 vertical_sync;
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u32 exit_line;
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u32 pipe_source;
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u32 pipe_border_color_pattern;
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u32 reserved;
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u32 vsync_shift;
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u32 pipe_mult;
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u32 dpll_reserved_dac_multiplier;
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u32 dpll_raw_dac_multiplier;
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u32 dpll_divisor_a0;
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u32 dpll_divisor_a1;
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u32 dpll_p1;
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u32 dpll_control;
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u32 m1_value;
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u32 n1_value;
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u32 m2_value;
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u32 n2_value;
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u32 m1_link;
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u32 n1_link;
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u32 m2_link;
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u32 n2_link;
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};
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ErrorOr<void> set_mode_setting_timings(Badge<IntelDisplayConnectorGroup>, DisplayConnector::ModeSetting const&);
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virtual ErrorOr<void> set_dpll_settings(Badge<IntelDisplayConnectorGroup>, IntelGraphics::PLLSettings const& settings, size_t dac_multiplier) = 0;
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virtual ErrorOr<void> enable_dpll_without_vga(Badge<IntelDisplayConnectorGroup>) = 0;
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virtual ErrorOr<void> disable_dpll(Badge<IntelDisplayConnectorGroup>) = 0;
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ShadowRegisters current_registers_state() const;
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virtual ~IntelDisplayTranscoder() = default;
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protected:
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struct [[gnu::packed]] TranscoderRegisters {
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u32 horizontal_total;
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u32 horizontal_blank;
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u32 horizontal_sync;
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u32 vertical_total;
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u32 vertical_blank;
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u32 vertical_sync;
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u32 exit_line;
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u32 pipe_source;
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u32 pipe_border_color_pattern;
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u32 reserved;
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u32 vsync_shift;
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u32 pipe_mult;
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u32 m1_value;
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u32 n1_value;
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u32 m2_value;
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u32 n2_value;
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u32 m1_link;
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u32 n1_link;
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u32 m2_link;
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u32 n2_link;
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};
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explicit IntelDisplayTranscoder(Memory::TypedMapping<TranscoderRegisters volatile>);
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mutable Spinlock<LockRank::None> m_access_lock;
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ShadowRegisters m_shadow_registers {};
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Memory::TypedMapping<TranscoderRegisters volatile> m_transcoder_registers;
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};
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}
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