0d934fc991
Alot of code is shared between i386/i686/x86 and x86_64 and a lot probably will be used for compatability modes. So we start by moving the headers into one Directory. We will probalby be able to move some cpp files aswell.
249 lines
7.3 KiB
C++
249 lines
7.3 KiB
C++
/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <AK/Assertions.h>
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#include <AK/Types.h>
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#include <Kernel/Arch/x86/CPU.h>
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#include <Kernel/IO.h>
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#include <Kernel/Interrupts/GenericInterruptHandler.h>
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#include <Kernel/Interrupts/PIC.h>
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namespace Kernel {
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// The slave 8259 is connected to the master's IRQ2 line.
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// This is really only to enhance clarity.
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#define SLAVE_INDEX 2
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#define PIC0_CTL 0x20
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#define PIC0_CMD 0x21
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#define PIC1_CTL 0xA0
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#define PIC1_CMD 0xA1
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#define ICW1_ICW4 0x01 // ICW4 (not) needed
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#define ICW1_SINGLE 0x02 // Single (cascade) mode
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#define ICW1_INTERVAL4 0x04 // Call address interval 4 (8)
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#define ICW1_LEVEL 0x08 // Level triggered (edge) mode
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#define ICW1_INIT 0x10 // Initialization - required
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#define ICW4_8086 0x01 // 8086/88 (MCS-80/85) mode
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#define ICW4_AUTO 0x02 // Auto (normal) EOI
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#define ICW4_BUF_SLAVE 0x08 // Buffered mode/slave
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#define ICW4_BUF_MASTER 0x0C // Buffered mode/master
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#define ICW4_SFNM 0x10 // Special fully nested (not)
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bool inline static is_all_masked(u16 reg)
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{
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return reg == 0xFFFF;
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}
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bool PIC::is_enabled() const
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{
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return !is_all_masked(m_cached_irq_mask) && !is_hard_disabled();
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}
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void PIC::disable(const GenericInterruptHandler& handler)
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{
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InterruptDisabler disabler;
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VERIFY(!is_hard_disabled());
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VERIFY(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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u8 irq = handler.interrupt_number();
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if (m_cached_irq_mask & (1 << irq))
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return;
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u8 imr;
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if (irq & 8) {
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imr = IO::in8(PIC1_CMD);
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imr |= 1 << (irq & 7);
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IO::out8(PIC1_CMD, imr);
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} else {
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imr = IO::in8(PIC0_CMD);
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imr |= 1 << irq;
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IO::out8(PIC0_CMD, imr);
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}
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m_cached_irq_mask |= 1 << irq;
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}
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UNMAP_AFTER_INIT PIC::PIC()
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{
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initialize();
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}
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void PIC::spurious_eoi(const GenericInterruptHandler& handler) const
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{
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VERIFY(handler.type() == HandlerType::SpuriousInterruptHandler);
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if (handler.interrupt_number() == 7)
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return;
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if (handler.interrupt_number() == 15) {
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IO::in8(PIC1_CMD); /* dummy read */
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IO::out8(PIC0_CTL, 0x60 | (2));
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}
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}
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bool PIC::is_vector_enabled(u8 irq) const
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{
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return m_cached_irq_mask & (1 << irq);
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}
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void PIC::enable(const GenericInterruptHandler& handler)
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{
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InterruptDisabler disabler;
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VERIFY(!is_hard_disabled());
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VERIFY(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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enable_vector(handler.interrupt_number());
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}
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void PIC::enable_vector(u8 irq)
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{
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InterruptDisabler disabler;
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VERIFY(!is_hard_disabled());
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if (!(m_cached_irq_mask & (1 << irq)))
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return;
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u8 imr;
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if (irq & 8) {
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imr = IO::in8(PIC1_CMD);
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imr &= ~(1 << (irq & 7));
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IO::out8(PIC1_CMD, imr);
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} else {
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imr = IO::in8(PIC0_CMD);
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imr &= ~(1 << irq);
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IO::out8(PIC0_CMD, imr);
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}
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m_cached_irq_mask &= ~(1 << irq);
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}
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void PIC::eoi(const GenericInterruptHandler& handler) const
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{
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InterruptDisabler disabler;
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VERIFY(!is_hard_disabled());
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u8 irq = handler.interrupt_number();
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VERIFY(irq >= gsi_base() && irq < interrupt_vectors_count());
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if ((1 << irq) & m_cached_irq_mask) {
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spurious_eoi(handler);
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return;
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}
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eoi_interrupt(irq);
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}
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void PIC::eoi_interrupt(u8 irq) const
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{
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if (irq & 8) {
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IO::in8(PIC1_CMD); /* dummy read */
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IO::out8(PIC1_CTL, 0x60 | (irq & 7));
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IO::out8(PIC0_CTL, 0x60 | (2));
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return;
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}
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IO::in8(PIC0_CMD); /* dummy read */
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IO::out8(PIC0_CTL, 0x60 | irq);
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}
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void PIC::complete_eoi() const
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{
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IO::out8(PIC1_CTL, 0x20);
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IO::out8(PIC0_CTL, 0x20);
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}
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void PIC::hard_disable()
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{
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InterruptDisabler disabler;
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remap(0x20);
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IO::out8(PIC0_CMD, 0xff);
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IO::out8(PIC1_CMD, 0xff);
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m_cached_irq_mask = 0xffff;
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IRQController::hard_disable();
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}
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void PIC::remap(u8 offset)
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{
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/* ICW1 (edge triggered mode, cascading controllers, expect ICW4) */
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IO::out8(PIC0_CTL, ICW1_INIT | ICW1_ICW4);
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IO::out8(PIC1_CTL, ICW1_INIT | ICW1_ICW4);
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/* ICW2 (upper 5 bits specify ISR indices, lower 3 idunno) */
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IO::out8(PIC0_CMD, offset);
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IO::out8(PIC1_CMD, offset + 0x08);
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/* ICW3 (configure master/slave relationship) */
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IO::out8(PIC0_CMD, 1 << SLAVE_INDEX);
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IO::out8(PIC1_CMD, SLAVE_INDEX);
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/* ICW4 (set x86 mode) */
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IO::out8(PIC0_CMD, ICW4_8086);
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IO::out8(PIC1_CMD, ICW4_8086);
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// Mask -- start out with all IRQs disabled.
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IO::out8(PIC0_CMD, 0xff);
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IO::out8(PIC1_CMD, 0xff);
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m_cached_irq_mask = 0xffff;
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// ...except IRQ2, since that's needed for the master to let through slave interrupts.
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enable_vector(2);
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}
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UNMAP_AFTER_INIT void PIC::initialize()
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{
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/* ICW1 (edge triggered mode, cascading controllers, expect ICW4) */
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IO::out8(PIC0_CTL, ICW1_INIT | ICW1_ICW4);
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IO::out8(PIC1_CTL, ICW1_INIT | ICW1_ICW4);
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/* ICW2 (upper 5 bits specify ISR indices, lower 3 idunno) */
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IO::out8(PIC0_CMD, IRQ_VECTOR_BASE);
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IO::out8(PIC1_CMD, IRQ_VECTOR_BASE + 0x08);
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/* ICW3 (configure master/slave relationship) */
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IO::out8(PIC0_CMD, 1 << SLAVE_INDEX);
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IO::out8(PIC1_CMD, SLAVE_INDEX);
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/* ICW4 (set x86 mode) */
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IO::out8(PIC0_CMD, ICW4_8086);
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IO::out8(PIC1_CMD, ICW4_8086);
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// Mask -- start out with all IRQs disabled.
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IO::out8(PIC0_CMD, 0xff);
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IO::out8(PIC1_CMD, 0xff);
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// ...except IRQ2, since that's needed for the master to let through slave interrupts.
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enable_vector(2);
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dmesgln("PIC: Cascading mode, vectors {:#02x}-{:#02x}", IRQ_VECTOR_BASE, IRQ_VECTOR_BASE + 0xf);
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}
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u16 PIC::get_isr() const
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{
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IO::out8(PIC0_CTL, 0x0b);
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IO::out8(PIC1_CTL, 0x0b);
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u8 isr0 = IO::in8(PIC0_CTL);
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u8 isr1 = IO::in8(PIC1_CTL);
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return (isr1 << 8) | isr0;
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}
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u16 PIC::get_irr() const
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{
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IO::out8(PIC0_CTL, 0x0a);
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IO::out8(PIC1_CTL, 0x0a);
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u8 irr0 = IO::in8(PIC0_CTL);
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u8 irr1 = IO::in8(PIC1_CTL);
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return (irr1 << 8) | irr0;
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}
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}
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