016fedbd20
Instead of doing that on the IntelDisplayPlane class, let's have this in derived classes so these classes can decide how to use the settings that were provided before calling the enable method.
381 lines
17 KiB
C++
381 lines
17 KiB
C++
/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Debug.h>
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#include <Kernel/Devices/DeviceManagement.h>
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#include <Kernel/Graphics/Console/ContiguousFramebufferConsole.h>
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#include <Kernel/Graphics/GraphicsManagement.h>
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#include <Kernel/Graphics/Intel/DisplayConnectorGroup.h>
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#include <Kernel/Graphics/Intel/Plane/G33DisplayPlane.h>
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#include <Kernel/Graphics/Intel/Transcoder/AnalogDisplayTranscoder.h>
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#include <Kernel/Memory/Region.h>
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#include <Kernel/Memory/TypedMapping.h>
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namespace Kernel {
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namespace IntelGraphics {
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static constexpr PLLMaxSettings G35Limits {
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{ 20'000'000, 400'000'000 }, // values in Hz, dot_clock
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{ 1'400'000'000, 2'800'000'000 }, // values in Hz, VCO
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{ 3, 8 }, // n
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{ 70, 120 }, // m
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{ 10, 20 }, // m1
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{ 5, 9 }, // m2
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{ 5, 80 }, // p
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{ 1, 8 }, // p1
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{ 5, 10 } // p2
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};
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}
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static bool check_pll_settings(IntelGraphics::PLLSettings const& settings, size_t reference_clock, IntelGraphics::PLLMaxSettings const& limits)
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{
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if (settings.n < limits.n.min || settings.n > limits.n.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "N is invalid {}", settings.n);
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return false;
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}
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if (settings.m1 < limits.m1.min || settings.m1 > limits.m1.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m1 is invalid {}", settings.m1);
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return false;
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}
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if (settings.m2 < limits.m2.min || settings.m2 > limits.m2.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m2 is invalid {}", settings.m2);
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return false;
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}
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if (settings.p1 < limits.p1.min || settings.p1 > limits.p1.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "p1 is invalid {}", settings.p1);
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return false;
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}
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if (settings.m1 <= settings.m2) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m2 is invalid {} as it is bigger than m1 {}", settings.m2, settings.m1);
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return false;
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}
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auto m = settings.compute_m();
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auto p = settings.compute_p();
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if (m < limits.m.min || m > limits.m.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "m invalid {}", m);
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return false;
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}
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if (p < limits.p.min || p > limits.p.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "p invalid {}", p);
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return false;
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}
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auto dot = settings.compute_dot_clock(reference_clock);
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auto vco = settings.compute_vco(reference_clock);
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if (dot < limits.dot_clock.min || dot > limits.dot_clock.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Dot clock invalid {}", dot);
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return false;
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}
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if (vco < limits.vco.min || vco > limits.vco.max) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "VCO clock invalid {}", vco);
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return false;
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}
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return true;
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}
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static size_t find_absolute_difference(u64 target_frequency, u64 checked_frequency)
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{
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if (target_frequency >= checked_frequency)
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return target_frequency - checked_frequency;
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return checked_frequency - target_frequency;
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}
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Optional<IntelGraphics::PLLSettings> IntelDisplayConnectorGroup::create_pll_settings(u64 target_frequency, u64 reference_clock, IntelGraphics::PLLMaxSettings const& limits)
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{
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IntelGraphics::PLLSettings settings;
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IntelGraphics::PLLSettings best_settings;
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// FIXME: Is this correct for all Intel Native graphics cards?
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settings.p2 = 10;
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Check PLL settings for ref clock of {} Hz, for target of {} Hz", reference_clock, target_frequency);
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u64 best_difference = 0xffffffff;
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for (settings.n = limits.n.min; settings.n <= limits.n.max; ++settings.n) {
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for (settings.m1 = limits.m1.max; settings.m1 >= limits.m1.min; --settings.m1) {
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for (settings.m2 = limits.m2.max; settings.m2 >= limits.m2.min; --settings.m2) {
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for (settings.p1 = limits.p1.max; settings.p1 >= limits.p1.min; --settings.p1) {
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Check PLL settings for {} {} {} {} {}", settings.n, settings.m1, settings.m2, settings.p1, settings.p2);
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if (!check_pll_settings(settings, reference_clock, limits))
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continue;
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auto current_dot_clock = settings.compute_dot_clock(reference_clock);
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if (current_dot_clock == target_frequency)
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return settings;
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auto difference = find_absolute_difference(target_frequency, current_dot_clock);
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if (difference < best_difference && (current_dot_clock > target_frequency)) {
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best_settings = settings;
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best_difference = difference;
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}
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}
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}
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}
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}
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if (best_settings.is_valid())
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return best_settings;
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return {};
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}
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ErrorOr<NonnullLockRefPtr<IntelDisplayConnectorGroup>> IntelDisplayConnectorGroup::try_create(Badge<IntelNativeGraphicsAdapter>, IntelGraphics::Generation generation, MMIORegion const& first_region, MMIORegion const& second_region)
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{
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auto registers_region = TRY(MM.allocate_kernel_region(first_region.pci_bar_paddr, first_region.pci_bar_space_length, "Intel Native Graphics Registers"sv, Memory::Region::Access::ReadWrite));
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// NOTE: 0x5100 is the offset of the start of the GMBus registers
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auto gmbus_connector = TRY(GMBusConnector::create_with_physical_address(first_region.pci_bar_paddr.offset(0x5100)));
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auto connector_group = TRY(adopt_nonnull_lock_ref_or_enomem(new (nothrow) IntelDisplayConnectorGroup(generation, move(gmbus_connector), move(registers_region), first_region, second_region)));
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TRY(connector_group->initialize_connectors());
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return connector_group;
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}
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IntelDisplayConnectorGroup::IntelDisplayConnectorGroup(IntelGraphics::Generation generation, NonnullOwnPtr<GMBusConnector> gmbus_connector, NonnullOwnPtr<Memory::Region> registers_region, MMIORegion const& first_region, MMIORegion const& second_region)
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: m_mmio_first_region(first_region)
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, m_mmio_second_region(second_region)
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, m_assigned_mmio_registers_region(m_mmio_first_region)
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, m_generation(generation)
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, m_registers_region(move(registers_region))
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, m_gmbus_connector(move(gmbus_connector))
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{
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}
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ErrorOr<void> IntelDisplayConnectorGroup::initialize_gen4_connectors()
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{
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// NOTE: Just assume we will need one Gen4 "transcoder"
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// NOTE: Main block of registers starting at HorizontalTotalA register (0x60000)
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auto transcoder_registers_paddr = m_mmio_first_region.pci_bar_paddr.offset(0x60000);
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// NOTE: Main block of Pipe registers starting at PipeA_DSL register (0x70000)
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auto pipe_registers_paddr = m_mmio_first_region.pci_bar_paddr.offset(0x70000);
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// NOTE: DPLL registers starting at DPLLDivisorA0 register (0x6040)
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auto dpll_registers_paddr = m_mmio_first_region.pci_bar_paddr.offset(0x6040);
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// NOTE: DPLL A control registers starting at 0x6014 (DPLL A Control register),
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// DPLL A Multiplier is at 0x601C, between them (at 0x6018) there is the DPLL B Control register.
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auto dpll_control_registers_paddr = m_mmio_first_region.pci_bar_paddr.offset(0x6014);
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m_transcoders[0] = TRY(IntelAnalogDisplayTranscoder::create_with_physical_addresses(transcoder_registers_paddr, pipe_registers_paddr, dpll_registers_paddr, dpll_control_registers_paddr));
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m_planes[0] = TRY(IntelG33DisplayPlane::create_with_physical_address(m_mmio_first_region.pci_bar_paddr.offset(0x70180)));
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Array<u8, 128> crt_edid_bytes {};
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{
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SpinlockLocker control_lock(m_control_lock);
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TRY(m_gmbus_connector->write(Graphics::ddc2_i2c_address, 0));
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TRY(m_gmbus_connector->read(Graphics::ddc2_i2c_address, crt_edid_bytes.data(), crt_edid_bytes.size()));
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}
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m_connectors[0] = TRY(IntelNativeDisplayConnector::try_create_with_display_connector_group(*this, IntelNativeDisplayConnector::ConnectorIndex::PortA, IntelNativeDisplayConnector::Type::Analog, m_mmio_second_region.pci_bar_paddr, m_mmio_second_region.pci_bar_space_length));
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m_connectors[0]->set_edid_bytes({}, crt_edid_bytes);
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return {};
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}
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ErrorOr<void> IntelDisplayConnectorGroup::initialize_connectors()
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{
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// NOTE: Intel Graphics Generation 4 is pretty ancient beast, and we should not
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// assume we can find a VBT for it. Just initialize the (assumed) CRT connector and be done with it.
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if (m_generation == IntelGraphics::Generation::Gen4) {
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TRY(initialize_gen4_connectors());
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} else {
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VERIFY_NOT_REACHED();
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}
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for (size_t connector_index = 0; connector_index < m_connectors.size(); connector_index++) {
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if (!m_connectors[connector_index])
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continue;
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if (!m_connectors[connector_index]->m_edid_valid)
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continue;
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TRY(m_connectors[connector_index]->set_safe_mode_setting());
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TRY(m_connectors[connector_index]->create_attached_framebuffer_console({}));
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}
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return {};
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}
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ErrorOr<void> IntelDisplayConnectorGroup::set_safe_mode_setting(Badge<IntelNativeDisplayConnector>, IntelNativeDisplayConnector& connector)
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{
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VERIFY(connector.m_modeset_lock.is_locked());
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if (!connector.m_edid_parser.has_value())
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return Error::from_errno(ENOTSUP);
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if (!connector.m_edid_parser.value().detailed_timing(0).has_value())
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return Error::from_errno(ENOTSUP);
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auto details = connector.m_edid_parser.value().detailed_timing(0).release_value();
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DisplayConnector::ModeSetting modesetting {
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// Note: We assume that we always use 32 bit framebuffers.
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.horizontal_stride = details.horizontal_addressable_pixels() * sizeof(u32),
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.pixel_clock_in_khz = details.pixel_clock_khz(),
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.horizontal_active = details.horizontal_addressable_pixels(),
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.horizontal_front_porch_pixels = details.horizontal_front_porch_pixels(),
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.horizontal_sync_time_pixels = details.horizontal_sync_pulse_width_pixels(),
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.horizontal_blank_pixels = details.horizontal_blanking_pixels(),
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.vertical_active = details.vertical_addressable_lines(),
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.vertical_front_porch_lines = details.vertical_front_porch_lines(),
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.vertical_sync_time_lines = details.vertical_sync_pulse_width_lines(),
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.vertical_blank_lines = details.vertical_blanking_lines(),
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.horizontal_offset = 0,
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.vertical_offset = 0,
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};
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return set_mode_setting(connector, modesetting);
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}
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ErrorOr<void> IntelDisplayConnectorGroup::set_mode_setting(Badge<IntelNativeDisplayConnector>, IntelNativeDisplayConnector& connector, DisplayConnector::ModeSetting const& mode_setting)
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{
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return set_mode_setting(connector, mode_setting);
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}
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ErrorOr<void> IntelDisplayConnectorGroup::set_mode_setting(IntelNativeDisplayConnector& connector, DisplayConnector::ModeSetting const& mode_setting)
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{
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VERIFY(connector.m_modeset_lock.is_locked());
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VERIFY(to_underlying(connector.connector_index()) < m_connectors.size());
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VERIFY(&connector == m_connectors[to_underlying(connector.connector_index())].ptr());
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DisplayConnector::ModeSetting actual_mode_setting = mode_setting;
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actual_mode_setting.horizontal_stride = actual_mode_setting.horizontal_active * sizeof(u32);
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VERIFY(actual_mode_setting.horizontal_stride != 0);
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if (m_generation == IntelGraphics::Generation::Gen4) {
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TRY(set_gen4_mode_setting(connector, actual_mode_setting));
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} else {
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VERIFY_NOT_REACHED();
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}
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connector.m_current_mode_setting = actual_mode_setting;
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if (!connector.m_framebuffer_console.is_null())
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static_cast<Graphics::GenericFramebufferConsoleImpl*>(connector.m_framebuffer_console.ptr())->set_resolution(actual_mode_setting.horizontal_active, actual_mode_setting.vertical_active, actual_mode_setting.horizontal_stride);
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return {};
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}
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ErrorOr<void> IntelDisplayConnectorGroup::set_gen4_mode_setting(IntelNativeDisplayConnector& connector, DisplayConnector::ModeSetting const& mode_setting)
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{
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VERIFY(connector.m_modeset_lock.is_locked());
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SpinlockLocker control_lock(m_control_lock);
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SpinlockLocker modeset_lock(m_modeset_lock);
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if (!set_crt_resolution(mode_setting))
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return Error::from_errno(ENOTSUP);
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return {};
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}
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void IntelDisplayConnectorGroup::enable_vga_plane()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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}
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StringView IntelDisplayConnectorGroup::convert_analog_output_register_to_string(AnalogOutputRegisterOffset index) const
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{
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switch (index) {
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case AnalogOutputRegisterOffset::AnalogDisplayPort:
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return "AnalogDisplayPort"sv;
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case AnalogOutputRegisterOffset::VGADisplayPlaneControl:
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return "VGADisplayPlaneControl"sv;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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void IntelDisplayConnectorGroup::write_to_general_register(RegisterOffset offset, u32 value)
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{
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VERIFY(m_control_lock.is_locked());
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SpinlockLocker lock(m_registers_lock);
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auto* reg = (u32 volatile*)m_registers_region->vaddr().offset(offset.value()).as_ptr();
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*reg = value;
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}
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u32 IntelDisplayConnectorGroup::read_from_general_register(RegisterOffset offset) const
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{
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VERIFY(m_control_lock.is_locked());
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SpinlockLocker lock(m_registers_lock);
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auto* reg = (u32 volatile*)m_registers_region->vaddr().offset(offset.value()).as_ptr();
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u32 value = *reg;
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return value;
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}
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void IntelDisplayConnectorGroup::write_to_analog_output_register(AnalogOutputRegisterOffset index, u32 value)
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{
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel Graphics Display Connector:: Write to {} value of {:x}", convert_analog_output_register_to_string(index), value);
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write_to_general_register(to_underlying(index), value);
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}
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u32 IntelDisplayConnectorGroup::read_from_analog_output_register(AnalogOutputRegisterOffset index) const
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{
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u32 value = read_from_general_register(to_underlying(index));
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel Graphics Display Connector: Read from {} value of {:x}", convert_analog_output_register_to_string(index), value);
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return value;
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}
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static size_t compute_dac_multiplier(size_t pixel_clock_in_khz)
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{
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel native graphics: Pixel clock is {} KHz", pixel_clock_in_khz);
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VERIFY(pixel_clock_in_khz >= 25000);
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if (pixel_clock_in_khz >= 100000) {
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return 1;
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} else if (pixel_clock_in_khz >= 50000) {
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return 2;
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} else {
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return 4;
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}
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}
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bool IntelDisplayConnectorGroup::set_crt_resolution(DisplayConnector::ModeSetting const& mode_setting)
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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// Note: Just in case we still allow access to VGA IO ports, disable it now.
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GraphicsManagement::the().disable_vga_emulation_access_permanently();
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auto dac_multiplier = compute_dac_multiplier(mode_setting.pixel_clock_in_khz);
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auto pll_settings = create_pll_settings((1000 * mode_setting.pixel_clock_in_khz * dac_multiplier), 96'000'000, IntelGraphics::G35Limits);
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if (!pll_settings.has_value())
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return false;
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auto settings = pll_settings.value();
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disable_dac_output();
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MUST(m_planes[0]->disable({}));
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MUST(m_transcoders[0]->disable_pipe({}));
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MUST(m_transcoders[0]->disable_dpll({}));
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disable_vga_emulation();
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dbgln_if(INTEL_GRAPHICS_DEBUG, "PLL settings for {} {} {} {} {}", settings.n, settings.m1, settings.m2, settings.p1, settings.p2);
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MUST(m_transcoders[0]->set_dpll_settings({}, settings, dac_multiplier));
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MUST(m_transcoders[0]->disable_dpll({}));
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MUST(m_transcoders[0]->enable_dpll_without_vga({}));
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MUST(m_transcoders[0]->set_mode_setting_timings({}, mode_setting));
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VERIFY(!m_transcoders[0]->pipe_enabled({}));
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MUST(m_transcoders[0]->enable_pipe({}));
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MUST(m_planes[0]->set_aperture_base({}, m_mmio_second_region.pci_bar_paddr));
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MUST(m_planes[0]->set_pipe({}, IntelDisplayPlane::PipeSelect::PipeA));
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MUST(m_planes[0]->set_horizontal_stride({}, mode_setting.horizontal_active * 4));
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MUST(m_planes[0]->set_horizontal_active_pixels_count({}, mode_setting.horizontal_active));
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// Note: This doesn't affect anything on the plane settings for Gen4, but we still
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// do it for the sake of "completeness".
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MUST(m_planes[0]->set_vertical_active_pixels_count({}, mode_setting.vertical_active));
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MUST(m_planes[0]->enable({}));
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enable_dac_output();
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return true;
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}
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void IntelDisplayConnectorGroup::disable_dac_output()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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write_to_analog_output_register(AnalogOutputRegisterOffset::AnalogDisplayPort, 0b11 << 10);
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}
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void IntelDisplayConnectorGroup::enable_dac_output()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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write_to_analog_output_register(AnalogOutputRegisterOffset::AnalogDisplayPort, (1 << 31));
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}
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void IntelDisplayConnectorGroup::disable_vga_emulation()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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write_to_analog_output_register(AnalogOutputRegisterOffset::VGADisplayPlaneControl, (1 << 31));
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read_from_analog_output_register(AnalogOutputRegisterOffset::VGADisplayPlaneControl);
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}
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}
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