IDEChannel.h 5.8 KB

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  1. /*
  2. * Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice, this
  9. * list of conditions and the following disclaimer.
  10. *
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  19. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  22. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  24. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. */
  26. //
  27. // Parallel ATA (PATA) controller driver
  28. //
  29. // This driver describes a logical PATA Channel. Each channel can connect up to 2
  30. // IDE Hard Disk Drives. The drives themselves can be either the master drive (hd0)
  31. // or the slave drive (hd1).
  32. //
  33. // More information about the ATA spec for PATA can be found here:
  34. // ftp://ftp.seagate.com/acrobat/reference/111-1c.pdf
  35. //
  36. #pragma once
  37. #include <AK/OwnPtr.h>
  38. #include <AK/RefPtr.h>
  39. #include <Kernel/Devices/Device.h>
  40. #include <Kernel/IO.h>
  41. #include <Kernel/Interrupts/IRQHandler.h>
  42. #include <Kernel/Lock.h>
  43. #include <Kernel/PhysicalAddress.h>
  44. #include <Kernel/Random.h>
  45. #include <Kernel/Storage/StorageDevice.h>
  46. #include <Kernel/VM/PhysicalPage.h>
  47. #include <Kernel/WaitQueue.h>
  48. namespace Kernel {
  49. class AsyncBlockDeviceRequest;
  50. struct PhysicalRegionDescriptor {
  51. PhysicalAddress offset;
  52. u16 size { 0 };
  53. u16 end_of_table { 0 };
  54. };
  55. class IDEController;
  56. class IDEChannel final : public IRQHandler {
  57. friend class IDEController;
  58. friend class PATADiskDevice;
  59. AK_MAKE_ETERNAL
  60. public:
  61. enum class ChannelType : u8 {
  62. Primary,
  63. Secondary
  64. };
  65. struct IOAddressGroup {
  66. IOAddressGroup(IOAddress io_base, IOAddress control_base, IOAddress bus_master_base)
  67. : m_io_base(io_base)
  68. , m_control_base(control_base)
  69. , m_bus_master_base(bus_master_base)
  70. {
  71. }
  72. // Disable default implementations that would use surprising integer promotion.
  73. bool operator==(const IOAddressGroup&) const = delete;
  74. bool operator<=(const IOAddressGroup&) const = delete;
  75. bool operator>=(const IOAddressGroup&) const = delete;
  76. bool operator<(const IOAddressGroup&) const = delete;
  77. bool operator>(const IOAddressGroup&) const = delete;
  78. IOAddress io_base() const { return m_io_base; };
  79. IOAddress control_base() const { return m_control_base; }
  80. IOAddress bus_master_base() const { return m_bus_master_base; }
  81. const IOAddressGroup& operator=(const IOAddressGroup& group)
  82. {
  83. m_io_base = group.io_base();
  84. m_control_base = group.control_base();
  85. m_bus_master_base = group.bus_master_base();
  86. return *this;
  87. }
  88. private:
  89. IOAddress m_io_base;
  90. IOAddress m_control_base;
  91. IOAddress m_bus_master_base;
  92. };
  93. public:
  94. static NonnullOwnPtr<IDEChannel> create(const IDEController&, IOAddressGroup, ChannelType type, bool force_pio);
  95. IDEChannel(const IDEController&, IOAddressGroup, ChannelType type, bool force_pio);
  96. virtual ~IDEChannel() override;
  97. RefPtr<StorageDevice> master_device() const;
  98. RefPtr<StorageDevice> slave_device() const;
  99. virtual const char* purpose() const override { return "PATA Channel"; }
  100. private:
  101. //^ IRQHandler
  102. virtual void handle_irq(const RegisterState&) override;
  103. enum class LBAMode : u8 {
  104. None, // CHS
  105. TwentyEightBit,
  106. FortyEightBit,
  107. };
  108. enum class Direction : u8 {
  109. Read,
  110. Write,
  111. };
  112. void initialize(bool force_pio);
  113. void detect_disks();
  114. String channel_type_string() const;
  115. void try_disambiguate_error();
  116. void wait_until_not_busy();
  117. void start_request(AsyncBlockDeviceRequest&, bool, bool, u16);
  118. void complete_current_request(AsyncDeviceRequest::RequestResult);
  119. void clear_pending_interrupts() const;
  120. void ata_access(Direction, bool, u32, u8, u16, bool);
  121. void ata_read_sectors_with_dma(bool, u16);
  122. void ata_read_sectors(bool, u16);
  123. bool ata_do_read_sector();
  124. void ata_write_sectors_with_dma(bool, u16);
  125. void ata_write_sectors(bool, u16);
  126. void ata_do_write_sector();
  127. // Data members
  128. ChannelType m_channel_type { ChannelType::Primary };
  129. volatile u8 m_device_error { 0 };
  130. PhysicalRegionDescriptor& prdt() { return *reinterpret_cast<PhysicalRegionDescriptor*>(m_prdt_page->paddr().offset(0xc0000000).as_ptr()); }
  131. RefPtr<PhysicalPage> m_prdt_page;
  132. RefPtr<PhysicalPage> m_dma_buffer_page;
  133. Lockable<bool> m_dma_enabled;
  134. EntropySource m_entropy_source;
  135. RefPtr<StorageDevice> m_master;
  136. RefPtr<StorageDevice> m_slave;
  137. AsyncBlockDeviceRequest* m_current_request { nullptr };
  138. u32 m_current_request_block_index { 0 };
  139. bool m_current_request_uses_dma { false };
  140. bool m_current_request_flushing_cache { false };
  141. SpinLock<u8> m_request_lock;
  142. IOAddressGroup m_io_group;
  143. NonnullRefPtr<IDEController> m_parent_controller;
  144. };
  145. }