IDEChannel.cpp 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583
  1. /*
  2. * Copyright (c) 2018-2021, Andreas Kling <kling@serenityos.org>
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice, this
  9. * list of conditions and the following disclaimer.
  10. *
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  19. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  22. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  24. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. */
  26. #include <AK/ByteBuffer.h>
  27. #include <AK/Singleton.h>
  28. #include <AK/StringView.h>
  29. #include <Kernel/FileSystem/ProcFS.h>
  30. #include <Kernel/IO.h>
  31. #include <Kernel/Process.h>
  32. #include <Kernel/Storage/ATA.h>
  33. #include <Kernel/Storage/IDEChannel.h>
  34. #include <Kernel/Storage/IDEController.h>
  35. #include <Kernel/Storage/PATADiskDevice.h>
  36. #include <Kernel/VM/MemoryManager.h>
  37. #include <Kernel/WorkQueue.h>
  38. namespace Kernel {
  39. #define PATA_PRIMARY_IRQ 14
  40. #define PATA_SECONDARY_IRQ 15
  41. #define PCI_Mass_Storage_Class 0x1
  42. #define PCI_IDE_Controller_Subclass 0x1
  43. UNMAP_AFTER_INIT NonnullOwnPtr<IDEChannel> IDEChannel::create(const IDEController& controller, IOAddressGroup io_group, ChannelType type, bool force_pio)
  44. {
  45. return make<IDEChannel>(controller, io_group, type, force_pio);
  46. }
  47. RefPtr<StorageDevice> IDEChannel::master_device() const
  48. {
  49. return m_master;
  50. }
  51. RefPtr<StorageDevice> IDEChannel::slave_device() const
  52. {
  53. return m_slave;
  54. }
  55. UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddressGroup io_group, ChannelType type, bool force_pio)
  56. : IRQHandler(type == ChannelType::Primary ? PATA_PRIMARY_IRQ : PATA_SECONDARY_IRQ)
  57. , m_channel_type(type)
  58. , m_io_group(io_group)
  59. , m_parent_controller(controller)
  60. {
  61. disable_irq();
  62. // FIXME: The device may not be capable of DMA.
  63. m_dma_enabled.resource() = !force_pio;
  64. ProcFS::add_sys_bool("ide_dma", m_dma_enabled);
  65. initialize(force_pio);
  66. detect_disks();
  67. // Note: calling to detect_disks could generate an interrupt, clear it if that's the case
  68. clear_pending_interrupts();
  69. enable_irq();
  70. }
  71. void IDEChannel::clear_pending_interrupts() const
  72. {
  73. m_io_group.io_base().offset(ATA_REG_STATUS).in<u8>();
  74. }
  75. UNMAP_AFTER_INIT IDEChannel::~IDEChannel()
  76. {
  77. }
  78. void IDEChannel::start_request(AsyncBlockDeviceRequest& request, bool use_dma, bool is_slave, u16 capabilities)
  79. {
  80. ScopedSpinLock lock(m_request_lock);
  81. dbgln_if(PATA_DEBUG, "IDEChannel::start_request");
  82. m_current_request = &request;
  83. m_current_request_block_index = 0;
  84. m_current_request_uses_dma = use_dma;
  85. m_current_request_flushing_cache = false;
  86. if (request.request_type() == AsyncBlockDeviceRequest::Read) {
  87. if (use_dma)
  88. ata_read_sectors_with_dma(is_slave, capabilities);
  89. else
  90. ata_read_sectors(is_slave, capabilities);
  91. } else {
  92. if (use_dma)
  93. ata_write_sectors_with_dma(is_slave, capabilities);
  94. else
  95. ata_write_sectors(is_slave, capabilities);
  96. }
  97. }
  98. void IDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult result)
  99. {
  100. // NOTE: this may be called from the interrupt handler!
  101. VERIFY(m_current_request);
  102. VERIFY(m_request_lock.is_locked());
  103. // Now schedule reading back the buffer as soon as we leave the irq handler.
  104. // This is important so that we can safely write the buffer back,
  105. // which could cause page faults. Note that this may be called immediately
  106. // before Processor::deferred_call_queue returns!
  107. g_io_work->queue([this, result]() {
  108. dbgln_if(PATA_DEBUG, "IDEChannel::complete_current_request result: {}", (int)result);
  109. ScopedSpinLock lock(m_request_lock);
  110. VERIFY(m_current_request);
  111. auto& request = *m_current_request;
  112. m_current_request = nullptr;
  113. if (m_current_request_uses_dma) {
  114. if (result == AsyncDeviceRequest::Success) {
  115. if (request.request_type() == AsyncBlockDeviceRequest::Read) {
  116. if (!request.write_to_buffer(request.buffer(), m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * request.block_count())) {
  117. lock.unlock();
  118. request.complete(AsyncDeviceRequest::MemoryFault);
  119. return;
  120. }
  121. }
  122. // I read somewhere that this may trigger a cache flush so let's do it.
  123. m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
  124. }
  125. }
  126. lock.unlock();
  127. request.complete(result);
  128. });
  129. }
  130. UNMAP_AFTER_INIT void IDEChannel::initialize(bool force_pio)
  131. {
  132. m_parent_controller->enable_pin_based_interrupts();
  133. dbgln_if(PATA_DEBUG, "IDEChannel: {} IO base: {}", channel_type_string(), m_io_group.io_base());
  134. dbgln_if(PATA_DEBUG, "IDEChannel: {} control base: {}", channel_type_string(), m_io_group.control_base());
  135. dbgln_if(PATA_DEBUG, "IDEChannel: {} bus master base: {}", channel_type_string(), m_io_group.bus_master_base());
  136. if (force_pio) {
  137. dbgln("IDEChannel: Requested to force PIO mode; not setting up DMA");
  138. return;
  139. }
  140. // Let's try to set up DMA transfers.
  141. PCI::enable_bus_mastering(m_parent_controller->pci_address());
  142. m_prdt_page = MM.allocate_supervisor_physical_page();
  143. prdt().end_of_table = 0x8000;
  144. m_dma_buffer_page = MM.allocate_supervisor_physical_page();
  145. }
  146. static void print_ide_status(u8 status)
  147. {
  148. dbgln("IDEChannel: print_ide_status: DRQ={} BSY={}, DRDY={}, DSC={}, DF={}, CORR={}, IDX={}, ERR={}",
  149. (status & ATA_SR_DRQ) != 0,
  150. (status & ATA_SR_BSY) != 0,
  151. (status & ATA_SR_DRDY) != 0,
  152. (status & ATA_SR_DSC) != 0,
  153. (status & ATA_SR_DF) != 0,
  154. (status & ATA_SR_CORR) != 0,
  155. (status & ATA_SR_IDX) != 0,
  156. (status & ATA_SR_ERR) != 0);
  157. }
  158. void IDEChannel::try_disambiguate_error()
  159. {
  160. dbgln("IDEChannel: Error cause:");
  161. switch (m_device_error) {
  162. case ATA_ER_BBK:
  163. dbgln("IDEChannel: - Bad block");
  164. break;
  165. case ATA_ER_UNC:
  166. dbgln("IDEChannel: - Uncorrectable data");
  167. break;
  168. case ATA_ER_MC:
  169. dbgln("IDEChannel: - Media changed");
  170. break;
  171. case ATA_ER_IDNF:
  172. dbgln("IDEChannel: - ID mark not found");
  173. break;
  174. case ATA_ER_MCR:
  175. dbgln("IDEChannel: - Media change request");
  176. break;
  177. case ATA_ER_ABRT:
  178. dbgln("IDEChannel: - Command aborted");
  179. break;
  180. case ATA_ER_TK0NF:
  181. dbgln("IDEChannel: - Track 0 not found");
  182. break;
  183. case ATA_ER_AMNF:
  184. dbgln("IDEChannel: - No address mark");
  185. break;
  186. default:
  187. dbgln("IDEChannel: - No one knows");
  188. break;
  189. }
  190. }
  191. void IDEChannel::handle_irq(const RegisterState&)
  192. {
  193. u8 status = m_io_group.io_base().offset(ATA_REG_STATUS).in<u8>();
  194. m_entropy_source.add_random_event(status);
  195. u8 bstatus = m_io_group.bus_master_base().offset(2).in<u8>();
  196. if (!(bstatus & 0x4)) {
  197. // interrupt not from this device, ignore
  198. dbgln_if(PATA_DEBUG, "IDEChannel: ignore interrupt");
  199. return;
  200. }
  201. ScopedSpinLock lock(m_request_lock);
  202. dbgln_if(PATA_DEBUG, "IDEChannel: interrupt: DRQ={}, BSY={}, DRDY={}",
  203. (status & ATA_SR_DRQ) != 0,
  204. (status & ATA_SR_BSY) != 0,
  205. (status & ATA_SR_DRDY) != 0);
  206. if (!m_current_request) {
  207. dbgln("IDEChannel: IRQ but no pending request!");
  208. return;
  209. }
  210. if (status & ATA_SR_ERR) {
  211. print_ide_status(status);
  212. m_device_error = m_io_group.io_base().offset(ATA_REG_ERROR).in<u8>();
  213. dbgln("IDEChannel: Error {:#02x}!", (u8)m_device_error);
  214. try_disambiguate_error();
  215. complete_current_request(AsyncDeviceRequest::Failure);
  216. return;
  217. }
  218. m_device_error = 0;
  219. if (m_current_request_uses_dma) {
  220. complete_current_request(AsyncDeviceRequest::Success);
  221. return;
  222. }
  223. // Now schedule reading/writing the buffer as soon as we leave the irq handler.
  224. // This is important so that we can safely access the buffers, which could
  225. // trigger page faults
  226. Processor::deferred_call_queue([this]() {
  227. ScopedSpinLock lock(m_request_lock);
  228. if (m_current_request->request_type() == AsyncBlockDeviceRequest::Read) {
  229. dbgln_if(PATA_DEBUG, "IDEChannel: Read block {}/{}", m_current_request_block_index, m_current_request->block_count());
  230. if (ata_do_read_sector()) {
  231. if (++m_current_request_block_index >= m_current_request->block_count()) {
  232. complete_current_request(AsyncDeviceRequest::Success);
  233. return;
  234. }
  235. // Wait for the next block
  236. enable_irq();
  237. }
  238. } else {
  239. if (!m_current_request_flushing_cache) {
  240. dbgln_if(PATA_DEBUG, "IDEChannel: Wrote block {}/{}", m_current_request_block_index, m_current_request->block_count());
  241. if (++m_current_request_block_index >= m_current_request->block_count()) {
  242. // We read the last block, flush cache
  243. VERIFY(!m_current_request_flushing_cache);
  244. m_current_request_flushing_cache = true;
  245. m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_CACHE_FLUSH);
  246. } else {
  247. // Read next block
  248. ata_do_write_sector();
  249. }
  250. } else {
  251. complete_current_request(AsyncDeviceRequest::Success);
  252. }
  253. }
  254. });
  255. }
  256. static void io_delay()
  257. {
  258. for (int i = 0; i < 4; ++i)
  259. IO::in8(0x3f6);
  260. }
  261. void IDEChannel::wait_until_not_busy()
  262. {
  263. while (m_io_group.control_base().in<u8>() & ATA_SR_BSY)
  264. ;
  265. }
  266. String IDEChannel::channel_type_string() const
  267. {
  268. if (m_channel_type == ChannelType::Primary)
  269. return "Primary";
  270. return "Secondary";
  271. }
  272. UNMAP_AFTER_INIT void IDEChannel::detect_disks()
  273. {
  274. auto channel_string = [](u8 i) -> const char* {
  275. if (i == 0)
  276. return "master";
  277. return "slave";
  278. };
  279. // There are only two possible disks connected to a channel
  280. for (auto i = 0; i < 2; i++) {
  281. m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(0xA0 | (i << 4)); // First, we need to select the drive itself
  282. m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_IDENTIFY); // Send the ATA_IDENTIFY command
  283. // Wait for the BSY flag to be reset
  284. while (m_io_group.control_base().in<u8>() & ATA_SR_BSY)
  285. ;
  286. if (m_io_group.control_base().in<u8>() == 0x00) {
  287. dbgln_if(PATA_DEBUG, "IDEChannel: No {} {} disk detected!", channel_type_string().to_lowercase(), channel_string(i));
  288. continue;
  289. }
  290. bool check_for_atapi = false;
  291. PATADiskDevice::InterfaceType interface_type = PATADiskDevice::InterfaceType::ATA;
  292. for (;;) {
  293. u8 status = m_io_group.control_base().in<u8>();
  294. if (status & ATA_SR_ERR) {
  295. dbgln_if(PATA_DEBUG, "IDEChannel: {} {} device is not ATA. Will check for ATAPI.", channel_type_string(), channel_string(i));
  296. check_for_atapi = true;
  297. break;
  298. }
  299. if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRQ)) {
  300. dbgln_if(PATA_DEBUG, "IDEChannel: {} {} device appears to be ATA.", channel_type_string(), channel_string(i));
  301. interface_type = PATADiskDevice::InterfaceType::ATA;
  302. break;
  303. }
  304. }
  305. if (check_for_atapi) {
  306. u8 cl = m_io_group.io_base().offset(ATA_REG_LBA1).in<u8>();
  307. u8 ch = m_io_group.io_base().offset(ATA_REG_LBA2).in<u8>();
  308. if ((cl == 0x14 && ch == 0xEB) || (cl == 0x69 && ch == 0x96)) {
  309. interface_type = PATADiskDevice::InterfaceType::ATAPI;
  310. dbgln("IDEChannel: {} {} device appears to be ATAPI. We're going to ignore it for now as we don't support it.", channel_type_string(), channel_string(i));
  311. continue;
  312. } else {
  313. dbgln("IDEChannel: {} {} device doesn't appear to be ATA or ATAPI. Ignoring it.", channel_type_string(), channel_string(i));
  314. continue;
  315. }
  316. }
  317. ByteBuffer wbuf = ByteBuffer::create_uninitialized(512);
  318. ByteBuffer bbuf = ByteBuffer::create_uninitialized(512);
  319. u8* b = bbuf.data();
  320. u16* w = (u16*)wbuf.data();
  321. for (u32 i = 0; i < 256; ++i) {
  322. u16 data = m_io_group.io_base().offset(ATA_REG_DATA).in<u16>();
  323. *(w++) = data;
  324. *(b++) = MSB(data);
  325. *(b++) = LSB(data);
  326. }
  327. // "Unpad" the device name string.
  328. for (u32 i = 93; i > 54 && bbuf[i] == ' '; --i)
  329. bbuf[i] = 0;
  330. volatile ATAIdentifyBlock& identify_block = (volatile ATAIdentifyBlock&)(*wbuf.data());
  331. u16 capabilities = identify_block.capabilites[0];
  332. // If the drive is so old that it doesn't support LBA, ignore it.
  333. if (!(capabilities & ATA_CAP_LBA))
  334. continue;
  335. u64 max_addressable_block = identify_block.max_28_bit_addressable_logical_sector;
  336. // if we support 48-bit LBA, use that value instead.
  337. if (identify_block.commands_and_feature_sets_supported[1] & (1 << 10))
  338. max_addressable_block = identify_block.user_addressable_logical_sectors_count;
  339. dbgln("IDEChannel: {} {} {} device found: Name={}, Capacity={}, Capabilities=0x{:04x}", channel_type_string(), channel_string(i), interface_type == PATADiskDevice::InterfaceType::ATA ? "ATA" : "ATAPI", ((char*)bbuf.data() + 54), max_addressable_block * 512, capabilities);
  340. if (i == 0) {
  341. m_master = PATADiskDevice::create(m_parent_controller, *this, PATADiskDevice::DriveType::Master, interface_type, capabilities, max_addressable_block);
  342. } else {
  343. m_slave = PATADiskDevice::create(m_parent_controller, *this, PATADiskDevice::DriveType::Slave, interface_type, capabilities, max_addressable_block);
  344. }
  345. }
  346. }
  347. void IDEChannel::ata_access(Direction direction, bool slave_request, u64 lba, u8 block_count, u16 capabilities, bool use_dma)
  348. {
  349. LBAMode lba_mode;
  350. u8 head = 0;
  351. VERIFY(capabilities & ATA_CAP_LBA);
  352. if (lba >= 0x10000000) {
  353. lba_mode = LBAMode::FortyEightBit;
  354. head = 0;
  355. } else {
  356. lba_mode = LBAMode::TwentyEightBit;
  357. head = (lba & 0xF000000) >> 24;
  358. }
  359. wait_until_not_busy();
  360. m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(0xE0 | (static_cast<u8>(slave_request) << 4) | head);
  361. if (lba_mode == LBAMode::FortyEightBit) {
  362. m_io_group.io_base().offset(ATA_REG_SECCOUNT1).out<u8>(0);
  363. m_io_group.io_base().offset(ATA_REG_LBA3).out<u8>((lba & 0xFF000000) >> 24);
  364. m_io_group.io_base().offset(ATA_REG_LBA4).out<u8>((lba & 0xFF00000000ull) >> 32);
  365. m_io_group.io_base().offset(ATA_REG_LBA5).out<u8>((lba & 0xFF0000000000ull) >> 40);
  366. }
  367. m_io_group.io_base().offset(ATA_REG_SECCOUNT0).out<u8>(block_count);
  368. m_io_group.io_base().offset(ATA_REG_LBA0).out<u8>((lba & 0x000000FF) >> 0);
  369. m_io_group.io_base().offset(ATA_REG_LBA1).out<u8>((lba & 0x0000FF00) >> 8);
  370. m_io_group.io_base().offset(ATA_REG_LBA2).out<u8>((lba & 0x00FF0000) >> 16);
  371. for (;;) {
  372. auto status = m_io_group.control_base().in<u8>();
  373. if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
  374. break;
  375. }
  376. if (lba_mode != LBAMode::FortyEightBit) {
  377. if (use_dma)
  378. m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA : ATA_CMD_WRITE_DMA);
  379. else
  380. m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO : ATA_CMD_WRITE_PIO);
  381. } else {
  382. if (use_dma)
  383. m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA_EXT : ATA_CMD_WRITE_DMA_EXT);
  384. else
  385. m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO_EXT : ATA_CMD_WRITE_PIO_EXT);
  386. }
  387. enable_irq();
  388. }
  389. void IDEChannel::ata_read_sectors_with_dma(bool slave_request, u16 capabilities)
  390. {
  391. auto& request = *m_current_request;
  392. auto lba = request.block_index();
  393. dbgln_if(PATA_DEBUG, "IDEChannel::ata_read_sectors_with_dma ({} x {})", lba, request.block_count());
  394. prdt().offset = m_dma_buffer_page->paddr();
  395. prdt().size = 512 * request.block_count();
  396. VERIFY(prdt().size <= PAGE_SIZE);
  397. // Stop bus master
  398. m_io_group.bus_master_base().out<u8>(0);
  399. // Write the PRDT location
  400. m_io_group.bus_master_base().offset(4).out(m_prdt_page->paddr().get());
  401. // Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
  402. m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
  403. // Set transfer direction
  404. m_io_group.bus_master_base().out<u8>(0x8);
  405. ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities, true);
  406. // Start bus master
  407. m_io_group.bus_master_base().out<u8>(0x9);
  408. }
  409. bool IDEChannel::ata_do_read_sector()
  410. {
  411. dbgln_if(PATA_DEBUG, "IDEChannel::ata_do_read_sector");
  412. auto& request = *m_current_request;
  413. auto out_buffer = request.buffer().offset(m_current_request_block_index * 512);
  414. ssize_t nwritten = request.write_to_buffer_buffered<512>(out_buffer, 512, [&](u8* buffer, size_t buffer_bytes) {
  415. for (size_t i = 0; i < buffer_bytes; i += sizeof(u16))
  416. *(u16*)&buffer[i] = IO::in16(m_io_group.io_base().offset(ATA_REG_DATA).get());
  417. return (ssize_t)buffer_bytes;
  418. });
  419. if (nwritten < 0) {
  420. // TODO: Do we need to abort the PATA read if this wasn't the last block?
  421. complete_current_request(AsyncDeviceRequest::MemoryFault);
  422. return false;
  423. }
  424. return true;
  425. }
  426. // FIXME: This doesn't quite work and locks up reading LBA 3.
  427. void IDEChannel::ata_read_sectors(bool slave_request, u16 capabilities)
  428. {
  429. auto& request = *m_current_request;
  430. VERIFY(request.block_count() <= 256);
  431. dbgln_if(PATA_DEBUG, "IDEChannel::ata_read_sectors");
  432. auto lba = request.block_index();
  433. dbgln_if(PATA_DEBUG, "IDEChannel: Reading {} sector(s) @ LBA {}", request.block_count(), lba);
  434. ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities, false);
  435. }
  436. void IDEChannel::ata_write_sectors_with_dma(bool slave_request, u16 capabilities)
  437. {
  438. auto& request = *m_current_request;
  439. auto lba = request.block_index();
  440. dbgln_if(PATA_DEBUG, "IDEChannel::ata_write_sectors_with_dma ({} x {})", lba, request.block_count());
  441. prdt().offset = m_dma_buffer_page->paddr();
  442. prdt().size = 512 * request.block_count();
  443. if (!request.read_from_buffer(request.buffer(), m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * request.block_count())) {
  444. complete_current_request(AsyncDeviceRequest::MemoryFault);
  445. return;
  446. }
  447. VERIFY(prdt().size <= PAGE_SIZE);
  448. // Stop bus master
  449. m_io_group.bus_master_base().out<u8>(0);
  450. // Write the PRDT location
  451. m_io_group.bus_master_base().offset(4).out<u32>(m_prdt_page->paddr().get());
  452. // Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
  453. m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
  454. ata_access(Direction::Write, slave_request, lba, request.block_count(), capabilities, true);
  455. // Start bus master
  456. m_io_group.bus_master_base().out<u8>(0x1);
  457. }
  458. void IDEChannel::ata_do_write_sector()
  459. {
  460. auto& request = *m_current_request;
  461. io_delay();
  462. while ((m_io_group.control_base().in<u8>() & ATA_SR_BSY) || !(m_io_group.control_base().in<u8>() & ATA_SR_DRQ))
  463. ;
  464. u8 status = m_io_group.control_base().in<u8>();
  465. VERIFY(status & ATA_SR_DRQ);
  466. auto in_buffer = request.buffer().offset(m_current_request_block_index * 512);
  467. dbgln_if(PATA_DEBUG, "IDEChannel: Writing 512 bytes (part {}) (status={:#02x})...", m_current_request_block_index, status);
  468. ssize_t nread = request.read_from_buffer_buffered<512>(in_buffer, 512, [&](const u8* buffer, size_t buffer_bytes) {
  469. for (size_t i = 0; i < buffer_bytes; i += sizeof(u16))
  470. IO::out16(m_io_group.io_base().offset(ATA_REG_DATA).get(), *(const u16*)&buffer[i]);
  471. return (ssize_t)buffer_bytes;
  472. });
  473. if (nread < 0)
  474. complete_current_request(AsyncDeviceRequest::MemoryFault);
  475. }
  476. // FIXME: I'm assuming this doesn't work based on the fact PIO read doesn't work.
  477. void IDEChannel::ata_write_sectors(bool slave_request, u16 capabilities)
  478. {
  479. auto& request = *m_current_request;
  480. VERIFY(request.block_count() <= 256);
  481. auto start_sector = request.block_index();
  482. u32 count = request.block_count();
  483. dbgln_if(PATA_DEBUG, "IDEChannel: Writing {} sector(s) @ LBA {}", count, start_sector);
  484. ata_access(Direction::Write, slave_request, start_sector, request.block_count(), capabilities, false);
  485. ata_do_write_sector();
  486. }
  487. }