E1000NetworkAdapter.cpp 16 KB

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  1. /*
  2. * Copyright (c) 2018-2021, Andreas Kling <kling@serenityos.org>
  3. *
  4. * SPDX-License-Identifier: BSD-2-Clause
  5. */
  6. #include <AK/MACAddress.h>
  7. #include <Kernel/Bus/PCI/API.h>
  8. #include <Kernel/Bus/PCI/IDs.h>
  9. #include <Kernel/Debug.h>
  10. #include <Kernel/Net/Intel/E1000NetworkAdapter.h>
  11. #include <Kernel/Net/NetworkingManagement.h>
  12. #include <Kernel/Sections.h>
  13. namespace Kernel {
  14. #define REG_CTRL 0x0000
  15. #define REG_STATUS 0x0008
  16. #define REG_EEPROM 0x0014
  17. #define REG_CTRL_EXT 0x0018
  18. #define REG_INTERRUPT_CAUSE_READ 0x00C0
  19. #define REG_INTERRUPT_RATE 0x00C4
  20. #define REG_INTERRUPT_MASK_SET 0x00D0
  21. #define REG_INTERRUPT_MASK_CLEAR 0x00D8
  22. #define REG_RCTRL 0x0100
  23. #define REG_RXDESCLO 0x2800
  24. #define REG_RXDESCHI 0x2804
  25. #define REG_RXDESCLEN 0x2808
  26. #define REG_RXDESCHEAD 0x2810
  27. #define REG_RXDESCTAIL 0x2818
  28. #define REG_TCTRL 0x0400
  29. #define REG_TXDESCLO 0x3800
  30. #define REG_TXDESCHI 0x3804
  31. #define REG_TXDESCLEN 0x3808
  32. #define REG_TXDESCHEAD 0x3810
  33. #define REG_TXDESCTAIL 0x3818
  34. #define REG_RDTR 0x2820 // RX Delay Timer Register
  35. #define REG_RXDCTL 0x3828 // RX Descriptor Control
  36. #define REG_RADV 0x282C // RX Int. Absolute Delay Timer
  37. #define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
  38. #define REG_TIPG 0x0410 // Transmit Inter Packet Gap
  39. #define ECTRL_SLU 0x40 // set link up
  40. #define RCTL_EN (1 << 1) // Receiver Enable
  41. #define RCTL_SBP (1 << 2) // Store Bad Packets
  42. #define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
  43. #define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
  44. #define RCTL_LPE (1 << 5) // Long Packet Reception Enable
  45. #define RCTL_LBM_NONE (0 << 6) // No Loopback
  46. #define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
  47. #define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
  48. #define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
  49. #define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
  50. #define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
  51. #define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
  52. #define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
  53. #define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
  54. #define RCTL_BAM (1 << 15) // Broadcast Accept Mode
  55. #define RCTL_VFE (1 << 18) // VLAN Filter Enable
  56. #define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
  57. #define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
  58. #define RCTL_DPF (1 << 22) // Discard Pause Frames
  59. #define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
  60. #define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
  61. // Buffer Sizes
  62. #define RCTL_BSIZE_256 (3 << 16)
  63. #define RCTL_BSIZE_512 (2 << 16)
  64. #define RCTL_BSIZE_1024 (1 << 16)
  65. #define RCTL_BSIZE_2048 (0 << 16)
  66. #define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
  67. #define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
  68. #define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
  69. // Transmit Command
  70. #define CMD_EOP (1 << 0) // End of Packet
  71. #define CMD_IFCS (1 << 1) // Insert FCS
  72. #define CMD_IC (1 << 2) // Insert Checksum
  73. #define CMD_RS (1 << 3) // Report Status
  74. #define CMD_RPS (1 << 4) // Report Packet Sent
  75. #define CMD_VLE (1 << 6) // VLAN Packet Enable
  76. #define CMD_IDE (1 << 7) // Interrupt Delay Enable
  77. // TCTL Register
  78. #define TCTL_EN (1 << 1) // Transmit Enable
  79. #define TCTL_PSP (1 << 3) // Pad Short Packets
  80. #define TCTL_CT_SHIFT 4 // Collision Threshold
  81. #define TCTL_COLD_SHIFT 12 // Collision Distance
  82. #define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
  83. #define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
  84. #define TSTA_DD (1 << 0) // Descriptor Done
  85. #define TSTA_EC (1 << 1) // Excess Collisions
  86. #define TSTA_LC (1 << 2) // Late Collision
  87. #define LSTA_TU (1 << 3) // Transmit Underrun
  88. // STATUS Register
  89. #define STATUS_FD 0x01
  90. #define STATUS_LU 0x02
  91. #define STATUS_TXOFF 0x08
  92. #define STATUS_SPEED 0xC0
  93. #define STATUS_SPEED_10MB 0x00
  94. #define STATUS_SPEED_100MB 0x40
  95. #define STATUS_SPEED_1000MB1 0x80
  96. #define STATUS_SPEED_1000MB2 0xC0
  97. // Interrupt Masks
  98. #define INTERRUPT_TXDW (1 << 0)
  99. #define INTERRUPT_TXQE (1 << 1)
  100. #define INTERRUPT_LSC (1 << 2)
  101. #define INTERRUPT_RXSEQ (1 << 3)
  102. #define INTERRUPT_RXDMT0 (1 << 4)
  103. #define INTERRUPT_RXO (1 << 6)
  104. #define INTERRUPT_RXT0 (1 << 7)
  105. #define INTERRUPT_MDAC (1 << 9)
  106. #define INTERRUPT_RXCFG (1 << 10)
  107. #define INTERRUPT_PHYINT (1 << 12)
  108. #define INTERRUPT_TXD_LOW (1 << 15)
  109. #define INTERRUPT_SRPD (1 << 16)
  110. // https://www.intel.com/content/dam/doc/manual/pci-pci-x-family-gbe-controllers-software-dev-manual.pdf Section 5.2
  111. UNMAP_AFTER_INIT static bool is_valid_device_id(u16 device_id)
  112. {
  113. // FIXME: It would be nice to distinguish which particular device it is.
  114. // Especially since it's needed to determine which registers we can access.
  115. // The reason I haven't done it now is because there's some IDs with multiple devices
  116. // and some devices with multiple IDs.
  117. switch (device_id) {
  118. case 0x1019: // 82547EI-A0, 82547EI-A1, 82547EI-B0, 82547GI-B0
  119. case 0x101A: // 82547EI-B0
  120. case 0x1010: // 82546EB-A1
  121. case 0x1012: // 82546EB-A1
  122. case 0x101D: // 82546EB-A1
  123. case 0x1079: // 82546GB-B0
  124. case 0x107A: // 82546GB-B0
  125. case 0x107B: // 82546GB-B0
  126. case 0x100F: // 82545EM-A
  127. case 0x1011: // 82545EM-A
  128. case 0x1026: // 82545GM-B
  129. case 0x1027: // 82545GM-B
  130. case 0x1028: // 82545GM-B
  131. case 0x1107: // 82544EI-A4
  132. case 0x1112: // 82544GC-A4
  133. case 0x1013: // 82541EI-A0, 82541EI-B0
  134. case 0x1018: // 82541EI-B0
  135. case 0x1076: // 82541GI-B1, 82541PI-C0
  136. case 0x1077: // 82541GI-B1
  137. case 0x1078: // 82541ER-C0
  138. case 0x1017: // 82540EP-A
  139. case 0x1016: // 82540EP-A
  140. case 0x100E: // 82540EM-A
  141. case 0x1015: // 82540EM-A
  142. return true;
  143. default:
  144. return false;
  145. }
  146. }
  147. UNMAP_AFTER_INIT ErrorOr<LockRefPtr<E1000NetworkAdapter>> E1000NetworkAdapter::try_to_initialize(PCI::DeviceIdentifier const& pci_device_identifier)
  148. {
  149. if (pci_device_identifier.hardware_id().vendor_id != PCI::VendorID::Intel)
  150. return nullptr;
  151. if (!is_valid_device_id(pci_device_identifier.hardware_id().device_id))
  152. return nullptr;
  153. u8 irq = pci_device_identifier.interrupt_line().value();
  154. auto interface_name = TRY(NetworkingManagement::generate_interface_name_from_pci_address(pci_device_identifier));
  155. auto registers_io_window = TRY(IOWindow::create_for_pci_device_bar(pci_device_identifier, PCI::HeaderType0BaseRegister::BAR0));
  156. auto adapter = TRY(adopt_nonnull_lock_ref_or_enomem(new (nothrow) E1000NetworkAdapter(pci_device_identifier.address(), irq, move(registers_io_window), move(interface_name))));
  157. adapter->m_rx_descriptors_region = TRY(MM.allocate_contiguous_kernel_region(TRY(Memory::page_round_up(sizeof(e1000_rx_desc) * number_of_rx_descriptors)), "E1000 RX Descriptors"sv, Memory::Region::Access::ReadWrite));
  158. adapter->m_tx_descriptors_region = TRY(MM.allocate_contiguous_kernel_region(TRY(Memory::page_round_up(sizeof(e1000_tx_desc) * number_of_tx_descriptors)), "E1000 TX Descriptors"sv, Memory::Region::Access::ReadWrite));
  159. if (!adapter->initialize())
  160. return Error::from_string_literal("E1000NetworkAdapter: Unable to initialize adapter");
  161. return adapter;
  162. }
  163. UNMAP_AFTER_INIT void E1000NetworkAdapter::setup_link()
  164. {
  165. u32 flags = in32(REG_CTRL);
  166. out32(REG_CTRL, flags | ECTRL_SLU);
  167. }
  168. UNMAP_AFTER_INIT void E1000NetworkAdapter::setup_interrupts()
  169. {
  170. out32(REG_INTERRUPT_RATE, 6000); // Interrupt rate of 1.536 milliseconds
  171. out32(REG_INTERRUPT_MASK_SET, INTERRUPT_LSC | INTERRUPT_RXT0 | INTERRUPT_RXO);
  172. in32(REG_INTERRUPT_CAUSE_READ);
  173. enable_irq();
  174. }
  175. UNMAP_AFTER_INIT bool E1000NetworkAdapter::initialize()
  176. {
  177. dmesgln_pci(*this, "Found @ {}", pci_address());
  178. enable_bus_mastering(pci_address());
  179. dmesgln_pci(*this, "IO base: {}", m_registers_io_window);
  180. dmesgln_pci(*this, "Interrupt line: {}", interrupt_number());
  181. detect_eeprom();
  182. dmesgln_pci(*this, "Has EEPROM? {}", m_has_eeprom);
  183. read_mac_address();
  184. auto const& mac = mac_address();
  185. dmesgln_pci(*this, "MAC address: {}", mac.to_string());
  186. initialize_rx_descriptors();
  187. initialize_tx_descriptors();
  188. setup_link();
  189. setup_interrupts();
  190. m_link_up = ((in32(REG_STATUS) & STATUS_LU) != 0);
  191. return true;
  192. }
  193. UNMAP_AFTER_INIT E1000NetworkAdapter::E1000NetworkAdapter(PCI::Address address, u8 irq, NonnullOwnPtr<IOWindow> registers_io_window, NonnullOwnPtr<KString> interface_name)
  194. : NetworkAdapter(move(interface_name))
  195. , PCI::Device(address)
  196. , IRQHandler(irq)
  197. , m_registers_io_window(move(registers_io_window))
  198. {
  199. }
  200. UNMAP_AFTER_INIT E1000NetworkAdapter::~E1000NetworkAdapter() = default;
  201. bool E1000NetworkAdapter::handle_irq(RegisterState const&)
  202. {
  203. u32 status = in32(REG_INTERRUPT_CAUSE_READ);
  204. m_entropy_source.add_random_event(status);
  205. if (status == 0)
  206. return false;
  207. if (status & INTERRUPT_LSC) {
  208. u32 flags = in32(REG_CTRL);
  209. out32(REG_CTRL, flags | ECTRL_SLU);
  210. m_link_up = ((in32(REG_STATUS) & STATUS_LU) != 0);
  211. }
  212. if (status & INTERRUPT_RXDMT0) {
  213. // Threshold OK?
  214. }
  215. if (status & INTERRUPT_RXO) {
  216. dbgln_if(E1000_DEBUG, "E1000: RX buffer overrun");
  217. }
  218. if (status & INTERRUPT_RXT0) {
  219. receive();
  220. }
  221. m_wait_queue.wake_all();
  222. out32(REG_INTERRUPT_CAUSE_READ, 0xffffffff);
  223. return true;
  224. }
  225. UNMAP_AFTER_INIT void E1000NetworkAdapter::detect_eeprom()
  226. {
  227. out32(REG_EEPROM, 0x1);
  228. for (int i = 0; i < 999; ++i) {
  229. u32 data = in32(REG_EEPROM);
  230. if (data & 0x10) {
  231. m_has_eeprom = true;
  232. return;
  233. }
  234. }
  235. m_has_eeprom = false;
  236. }
  237. UNMAP_AFTER_INIT u32 E1000NetworkAdapter::read_eeprom(u8 address)
  238. {
  239. u16 data = 0;
  240. u32 tmp = 0;
  241. if (m_has_eeprom) {
  242. out32(REG_EEPROM, ((u32)address << 8) | 1);
  243. while (!((tmp = in32(REG_EEPROM)) & (1 << 4)))
  244. ;
  245. } else {
  246. out32(REG_EEPROM, ((u32)address << 2) | 1);
  247. while (!((tmp = in32(REG_EEPROM)) & (1 << 1)))
  248. ;
  249. }
  250. data = (tmp >> 16) & 0xffff;
  251. return data;
  252. }
  253. UNMAP_AFTER_INIT void E1000NetworkAdapter::read_mac_address()
  254. {
  255. if (m_has_eeprom) {
  256. MACAddress mac {};
  257. u32 tmp = read_eeprom(0);
  258. mac[0] = tmp & 0xff;
  259. mac[1] = tmp >> 8;
  260. tmp = read_eeprom(1);
  261. mac[2] = tmp & 0xff;
  262. mac[3] = tmp >> 8;
  263. tmp = read_eeprom(2);
  264. mac[4] = tmp & 0xff;
  265. mac[5] = tmp >> 8;
  266. set_mac_address(mac);
  267. } else {
  268. VERIFY_NOT_REACHED();
  269. }
  270. }
  271. UNMAP_AFTER_INIT void E1000NetworkAdapter::initialize_rx_descriptors()
  272. {
  273. auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
  274. constexpr auto rx_buffer_size = 8192;
  275. constexpr auto rx_buffer_page_count = rx_buffer_size / PAGE_SIZE;
  276. m_rx_buffer_region = MM.allocate_contiguous_kernel_region(rx_buffer_size * number_of_rx_descriptors, "E1000 RX buffers"sv, Memory::Region::Access::ReadWrite).release_value();
  277. for (size_t i = 0; i < number_of_rx_descriptors; ++i) {
  278. auto& descriptor = rx_descriptors[i];
  279. m_rx_buffers[i] = m_rx_buffer_region->vaddr().as_ptr() + rx_buffer_size * i;
  280. descriptor.addr = m_rx_buffer_region->physical_page(rx_buffer_page_count * i)->paddr().get();
  281. descriptor.status = 0;
  282. }
  283. out32(REG_RXDESCLO, m_rx_descriptors_region->physical_page(0)->paddr().get());
  284. out32(REG_RXDESCHI, 0);
  285. out32(REG_RXDESCLEN, number_of_rx_descriptors * sizeof(e1000_rx_desc));
  286. out32(REG_RXDESCHEAD, 0);
  287. out32(REG_RXDESCTAIL, number_of_rx_descriptors - 1);
  288. out32(REG_RCTRL, RCTL_EN | RCTL_SBP | RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
  289. }
  290. UNMAP_AFTER_INIT void E1000NetworkAdapter::initialize_tx_descriptors()
  291. {
  292. auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
  293. constexpr auto tx_buffer_size = 8192;
  294. constexpr auto tx_buffer_page_count = tx_buffer_size / PAGE_SIZE;
  295. m_tx_buffer_region = MM.allocate_contiguous_kernel_region(tx_buffer_size * number_of_tx_descriptors, "E1000 TX buffers"sv, Memory::Region::Access::ReadWrite).release_value();
  296. for (size_t i = 0; i < number_of_tx_descriptors; ++i) {
  297. auto& descriptor = tx_descriptors[i];
  298. m_tx_buffers[i] = m_tx_buffer_region->vaddr().as_ptr() + tx_buffer_size * i;
  299. descriptor.addr = m_tx_buffer_region->physical_page(tx_buffer_page_count * i)->paddr().get();
  300. descriptor.cmd = 0;
  301. }
  302. out32(REG_TXDESCLO, m_tx_descriptors_region->physical_page(0)->paddr().get());
  303. out32(REG_TXDESCHI, 0);
  304. out32(REG_TXDESCLEN, number_of_tx_descriptors * sizeof(e1000_tx_desc));
  305. out32(REG_TXDESCHEAD, 0);
  306. out32(REG_TXDESCTAIL, 0);
  307. out32(REG_TCTRL, in32(REG_TCTRL) | TCTL_EN | TCTL_PSP);
  308. out32(REG_TIPG, 0x0060200A);
  309. }
  310. void E1000NetworkAdapter::out8(u16 address, u8 data)
  311. {
  312. dbgln_if(E1000_DEBUG, "E1000: OUT8 {:#02x} @ {:#04x}", data, address);
  313. m_registers_io_window->write8(address, data);
  314. }
  315. void E1000NetworkAdapter::out16(u16 address, u16 data)
  316. {
  317. dbgln_if(E1000_DEBUG, "E1000: OUT16 {:#04x} @ {:#04x}", data, address);
  318. m_registers_io_window->write16(address, data);
  319. }
  320. void E1000NetworkAdapter::out32(u16 address, u32 data)
  321. {
  322. dbgln_if(E1000_DEBUG, "E1000: OUT32 {:#08x} @ {:#04x}", data, address);
  323. m_registers_io_window->write32(address, data);
  324. }
  325. u8 E1000NetworkAdapter::in8(u16 address)
  326. {
  327. dbgln_if(E1000_DEBUG, "E1000: IN8 @ {:#04x}", address);
  328. return m_registers_io_window->read8(address);
  329. }
  330. u16 E1000NetworkAdapter::in16(u16 address)
  331. {
  332. dbgln_if(E1000_DEBUG, "E1000: IN16 @ {:#04x}", address);
  333. return m_registers_io_window->read16(address);
  334. }
  335. u32 E1000NetworkAdapter::in32(u16 address)
  336. {
  337. dbgln_if(E1000_DEBUG, "E1000: IN32 @ {:#04x}", address);
  338. return m_registers_io_window->read32(address);
  339. }
  340. void E1000NetworkAdapter::send_raw(ReadonlyBytes payload)
  341. {
  342. disable_irq();
  343. size_t tx_current = in32(REG_TXDESCTAIL) % number_of_tx_descriptors;
  344. dbgln_if(E1000_DEBUG, "E1000: Sending packet ({} bytes)", payload.size());
  345. auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
  346. auto& descriptor = tx_descriptors[tx_current];
  347. VERIFY(payload.size() <= 8192);
  348. auto* vptr = (void*)m_tx_buffers[tx_current];
  349. memcpy(vptr, payload.data(), payload.size());
  350. descriptor.length = payload.size();
  351. descriptor.status = 0;
  352. descriptor.cmd = CMD_EOP | CMD_IFCS | CMD_RS;
  353. dbgln_if(E1000_DEBUG, "E1000: Using tx descriptor {} (head is at {})", tx_current, in32(REG_TXDESCHEAD));
  354. tx_current = (tx_current + 1) % number_of_tx_descriptors;
  355. Processor::disable_interrupts();
  356. enable_irq();
  357. out32(REG_TXDESCTAIL, tx_current);
  358. for (;;) {
  359. if (descriptor.status) {
  360. Processor::enable_interrupts();
  361. break;
  362. }
  363. m_wait_queue.wait_forever("E1000NetworkAdapter"sv);
  364. }
  365. dbgln_if(E1000_DEBUG, "E1000: Sent packet, status is now {:#02x}!", (u8)descriptor.status);
  366. }
  367. void E1000NetworkAdapter::receive()
  368. {
  369. auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
  370. u32 rx_current;
  371. for (;;) {
  372. rx_current = in32(REG_RXDESCTAIL) % number_of_rx_descriptors;
  373. rx_current = (rx_current + 1) % number_of_rx_descriptors;
  374. if (!(rx_descriptors[rx_current].status & 1))
  375. break;
  376. auto* buffer = m_rx_buffers[rx_current];
  377. u16 length = rx_descriptors[rx_current].length;
  378. VERIFY(length <= 8192);
  379. dbgln_if(E1000_DEBUG, "E1000: Received 1 packet @ {:p} ({} bytes)", buffer, length);
  380. did_receive({ buffer, length });
  381. rx_descriptors[rx_current].status = 0;
  382. out32(REG_RXDESCTAIL, rx_current);
  383. }
  384. }
  385. i32 E1000NetworkAdapter::link_speed()
  386. {
  387. if (!link_up())
  388. return NetworkAdapter::LINKSPEED_INVALID;
  389. u32 speed = in32(REG_STATUS) & STATUS_SPEED;
  390. switch (speed) {
  391. case STATUS_SPEED_10MB:
  392. return 10;
  393. case STATUS_SPEED_100MB:
  394. return 100;
  395. case STATUS_SPEED_1000MB1:
  396. case STATUS_SPEED_1000MB2:
  397. return 1000;
  398. default:
  399. return NetworkAdapter::LINKSPEED_INVALID;
  400. }
  401. }
  402. bool E1000NetworkAdapter::link_full_duplex()
  403. {
  404. u32 status = in32(REG_STATUS);
  405. return !!(status & STATUS_FD);
  406. }
  407. }