E1000NetworkAdapter.cpp 17 KB

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  1. /*
  2. * Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice, this
  9. * list of conditions and the following disclaimer.
  10. *
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  19. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  22. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  24. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. */
  26. #include <AK/MACAddress.h>
  27. #include <Kernel/Debug.h>
  28. #include <Kernel/IO.h>
  29. #include <Kernel/Net/E1000NetworkAdapter.h>
  30. #include <Kernel/Thread.h>
  31. namespace Kernel {
  32. #define REG_CTRL 0x0000
  33. #define REG_STATUS 0x0008
  34. #define REG_EEPROM 0x0014
  35. #define REG_CTRL_EXT 0x0018
  36. #define REG_INTERRUPT_CAUSE_READ 0x00C0
  37. #define REG_INTERRUPT_RATE 0x00C4
  38. #define REG_INTERRUPT_MASK_SET 0x00D0
  39. #define REG_INTERRUPT_MASK_CLEAR 0x00D8
  40. #define REG_RCTRL 0x0100
  41. #define REG_RXDESCLO 0x2800
  42. #define REG_RXDESCHI 0x2804
  43. #define REG_RXDESCLEN 0x2808
  44. #define REG_RXDESCHEAD 0x2810
  45. #define REG_RXDESCTAIL 0x2818
  46. #define REG_TCTRL 0x0400
  47. #define REG_TXDESCLO 0x3800
  48. #define REG_TXDESCHI 0x3804
  49. #define REG_TXDESCLEN 0x3808
  50. #define REG_TXDESCHEAD 0x3810
  51. #define REG_TXDESCTAIL 0x3818
  52. #define REG_RDTR 0x2820 // RX Delay Timer Register
  53. #define REG_RXDCTL 0x3828 // RX Descriptor Control
  54. #define REG_RADV 0x282C // RX Int. Absolute Delay Timer
  55. #define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
  56. #define REG_TIPG 0x0410 // Transmit Inter Packet Gap
  57. #define ECTRL_SLU 0x40 //set link up
  58. #define RCTL_EN (1 << 1) // Receiver Enable
  59. #define RCTL_SBP (1 << 2) // Store Bad Packets
  60. #define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
  61. #define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
  62. #define RCTL_LPE (1 << 5) // Long Packet Reception Enable
  63. #define RCTL_LBM_NONE (0 << 6) // No Loopback
  64. #define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
  65. #define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
  66. #define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
  67. #define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
  68. #define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
  69. #define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
  70. #define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
  71. #define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
  72. #define RCTL_BAM (1 << 15) // Broadcast Accept Mode
  73. #define RCTL_VFE (1 << 18) // VLAN Filter Enable
  74. #define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
  75. #define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
  76. #define RCTL_DPF (1 << 22) // Discard Pause Frames
  77. #define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
  78. #define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
  79. // Buffer Sizes
  80. #define RCTL_BSIZE_256 (3 << 16)
  81. #define RCTL_BSIZE_512 (2 << 16)
  82. #define RCTL_BSIZE_1024 (1 << 16)
  83. #define RCTL_BSIZE_2048 (0 << 16)
  84. #define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
  85. #define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
  86. #define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
  87. // Transmit Command
  88. #define CMD_EOP (1 << 0) // End of Packet
  89. #define CMD_IFCS (1 << 1) // Insert FCS
  90. #define CMD_IC (1 << 2) // Insert Checksum
  91. #define CMD_RS (1 << 3) // Report Status
  92. #define CMD_RPS (1 << 4) // Report Packet Sent
  93. #define CMD_VLE (1 << 6) // VLAN Packet Enable
  94. #define CMD_IDE (1 << 7) // Interrupt Delay Enable
  95. // TCTL Register
  96. #define TCTL_EN (1 << 1) // Transmit Enable
  97. #define TCTL_PSP (1 << 3) // Pad Short Packets
  98. #define TCTL_CT_SHIFT 4 // Collision Threshold
  99. #define TCTL_COLD_SHIFT 12 // Collision Distance
  100. #define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
  101. #define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
  102. #define TSTA_DD (1 << 0) // Descriptor Done
  103. #define TSTA_EC (1 << 1) // Excess Collisions
  104. #define TSTA_LC (1 << 2) // Late Collision
  105. #define LSTA_TU (1 << 3) // Transmit Underrun
  106. // STATUS Register
  107. #define STATUS_FD 0x01
  108. #define STATUS_LU 0x02
  109. #define STATUS_TXOFF 0x08
  110. #define STATUS_SPEED 0xC0
  111. #define STATUS_SPEED_10MB 0x00
  112. #define STATUS_SPEED_100MB 0x40
  113. #define STATUS_SPEED_1000MB1 0x80
  114. #define STATUS_SPEED_1000MB2 0xC0
  115. // Interrupt Masks
  116. #define INTERRUPT_TXDW (1 << 0)
  117. #define INTERRUPT_TXQE (1 << 1)
  118. #define INTERRUPT_LSC (1 << 2)
  119. #define INTERRUPT_RXSEQ (1 << 3)
  120. #define INTERRUPT_RXDMT0 (1 << 4)
  121. #define INTERRUPT_RXO (1 << 6)
  122. #define INTERRUPT_RXT0 (1 << 7)
  123. #define INTERRUPT_MDAC (1 << 9)
  124. #define INTERRUPT_RXCFG (1 << 10)
  125. #define INTERRUPT_PHYINT (1 << 12)
  126. #define INTERRUPT_TXD_LOW (1 << 15)
  127. #define INTERRUPT_SRPD (1 << 16)
  128. // https://www.intel.com/content/dam/doc/manual/pci-pci-x-family-gbe-controllers-software-dev-manual.pdf Section 5.2
  129. static bool is_valid_device_id(u16 device_id)
  130. {
  131. // FIXME: It would be nice to distinguish which particular device it is.
  132. // Especially since it's needed to determine which registers we can access.
  133. // The reason I haven't done it now is because there's some IDs with multiple devices
  134. // and some devices with multiple IDs.
  135. switch (device_id) {
  136. case 0x1019: // 82547EI-A0, 82547EI-A1, 82547EI-B0, 82547GI-B0
  137. case 0x101A: // 82547EI-B0
  138. case 0x1010: // 82546EB-A1
  139. case 0x1012: // 82546EB-A1
  140. case 0x101D: // 82546EB-A1
  141. case 0x1079: // 82546GB-B0
  142. case 0x107A: // 82546GB-B0
  143. case 0x107B: // 82546GB-B0
  144. case 0x100F: // 82545EM-A
  145. case 0x1011: // 82545EM-A
  146. case 0x1026: // 82545GM-B
  147. case 0x1027: // 82545GM-B
  148. case 0x1028: // 82545GM-B
  149. case 0x1107: // 82544EI-A4
  150. case 0x1112: // 82544GC-A4
  151. case 0x1013: // 82541EI-A0, 82541EI-B0
  152. case 0x1018: // 82541EI-B0
  153. case 0x1076: // 82541GI-B1, 82541PI-C0
  154. case 0x1077: // 82541GI-B1
  155. case 0x1078: // 82541ER-C0
  156. case 0x1017: // 82540EP-A
  157. case 0x1016: // 82540EP-A
  158. case 0x100E: // 82540EM-A
  159. case 0x1015: // 82540EM-A
  160. return true;
  161. default:
  162. return false;
  163. }
  164. }
  165. UNMAP_AFTER_INIT void E1000NetworkAdapter::detect()
  166. {
  167. PCI::enumerate([&](const PCI::Address& address, PCI::ID id) {
  168. if (address.is_null())
  169. return;
  170. if (id.vendor_id != 0x8086)
  171. return;
  172. if (!is_valid_device_id(id.device_id))
  173. return;
  174. u8 irq = PCI::get_interrupt_line(address);
  175. [[maybe_unused]] auto& unused = adopt(*new E1000NetworkAdapter(address, irq)).leak_ref();
  176. });
  177. }
  178. UNMAP_AFTER_INIT E1000NetworkAdapter::E1000NetworkAdapter(PCI::Address address, u8 irq)
  179. : PCI::Device(address, irq)
  180. , m_io_base(PCI::get_BAR1(pci_address()) & ~1)
  181. , m_rx_descriptors_region(MM.allocate_contiguous_kernel_region(page_round_up(sizeof(e1000_rx_desc) * number_of_rx_descriptors + 16), "E1000 RX", Region::Access::Read | Region::Access::Write))
  182. , m_tx_descriptors_region(MM.allocate_contiguous_kernel_region(page_round_up(sizeof(e1000_tx_desc) * number_of_tx_descriptors + 16), "E1000 TX", Region::Access::Read | Region::Access::Write))
  183. {
  184. set_interface_name("e1k");
  185. klog() << "E1000: Found @ " << pci_address();
  186. enable_bus_mastering(pci_address());
  187. size_t mmio_base_size = PCI::get_BAR_space_size(pci_address(), 0);
  188. m_mmio_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of(PCI::get_BAR0(pci_address()))), page_round_up(mmio_base_size), "E1000 MMIO", Region::Access::Read | Region::Access::Write, Region::Cacheable::No);
  189. m_mmio_base = m_mmio_region->vaddr();
  190. m_use_mmio = true;
  191. m_interrupt_line = PCI::get_interrupt_line(pci_address());
  192. klog() << "E1000: port base: " << m_io_base;
  193. klog() << "E1000: MMIO base: " << PhysicalAddress(PCI::get_BAR0(pci_address()) & 0xfffffffc);
  194. klog() << "E1000: MMIO base size: " << mmio_base_size << " bytes";
  195. klog() << "E1000: Interrupt line: " << m_interrupt_line;
  196. detect_eeprom();
  197. klog() << "E1000: Has EEPROM? " << m_has_eeprom;
  198. read_mac_address();
  199. const auto& mac = mac_address();
  200. klog() << "E1000: MAC address: " << mac.to_string();
  201. u32 flags = in32(REG_CTRL);
  202. out32(REG_CTRL, flags | ECTRL_SLU);
  203. out32(REG_INTERRUPT_RATE, 6000); // Interrupt rate of 1.536 milliseconds
  204. initialize_rx_descriptors();
  205. initialize_tx_descriptors();
  206. out32(REG_INTERRUPT_MASK_SET, 0x1f6dc);
  207. out32(REG_INTERRUPT_MASK_SET, INTERRUPT_LSC | INTERRUPT_RXT0);
  208. in32(REG_INTERRUPT_CAUSE_READ);
  209. enable_irq();
  210. }
  211. UNMAP_AFTER_INIT E1000NetworkAdapter::~E1000NetworkAdapter()
  212. {
  213. }
  214. void E1000NetworkAdapter::handle_irq(const RegisterState&)
  215. {
  216. out32(REG_INTERRUPT_MASK_CLEAR, 0xffffffff);
  217. u32 status = in32(REG_INTERRUPT_CAUSE_READ);
  218. m_entropy_source.add_random_event(status);
  219. if (status & 4) {
  220. u32 flags = in32(REG_CTRL);
  221. out32(REG_CTRL, flags | ECTRL_SLU);
  222. }
  223. if (status & 0x80) {
  224. receive();
  225. }
  226. if (status & 0x10) {
  227. // Threshold OK?
  228. }
  229. m_wait_queue.wake_all();
  230. out32(REG_INTERRUPT_MASK_SET, INTERRUPT_LSC | INTERRUPT_RXT0 | INTERRUPT_RXO);
  231. }
  232. UNMAP_AFTER_INIT void E1000NetworkAdapter::detect_eeprom()
  233. {
  234. out32(REG_EEPROM, 0x1);
  235. for (int i = 0; i < 999; ++i) {
  236. u32 data = in32(REG_EEPROM);
  237. if (data & 0x10) {
  238. m_has_eeprom = true;
  239. return;
  240. }
  241. }
  242. m_has_eeprom = false;
  243. }
  244. UNMAP_AFTER_INIT u32 E1000NetworkAdapter::read_eeprom(u8 address)
  245. {
  246. u16 data = 0;
  247. u32 tmp = 0;
  248. if (m_has_eeprom) {
  249. out32(REG_EEPROM, ((u32)address << 8) | 1);
  250. while (!((tmp = in32(REG_EEPROM)) & (1 << 4)))
  251. ;
  252. } else {
  253. out32(REG_EEPROM, ((u32)address << 2) | 1);
  254. while (!((tmp = in32(REG_EEPROM)) & (1 << 1)))
  255. ;
  256. }
  257. data = (tmp >> 16) & 0xffff;
  258. return data;
  259. }
  260. UNMAP_AFTER_INIT void E1000NetworkAdapter::read_mac_address()
  261. {
  262. if (m_has_eeprom) {
  263. MACAddress mac {};
  264. u32 tmp = read_eeprom(0);
  265. mac[0] = tmp & 0xff;
  266. mac[1] = tmp >> 8;
  267. tmp = read_eeprom(1);
  268. mac[2] = tmp & 0xff;
  269. mac[3] = tmp >> 8;
  270. tmp = read_eeprom(2);
  271. mac[4] = tmp & 0xff;
  272. mac[5] = tmp >> 8;
  273. set_mac_address(mac);
  274. } else {
  275. VERIFY_NOT_REACHED();
  276. }
  277. }
  278. bool E1000NetworkAdapter::link_up()
  279. {
  280. return (in32(REG_STATUS) & STATUS_LU);
  281. }
  282. UNMAP_AFTER_INIT void E1000NetworkAdapter::initialize_rx_descriptors()
  283. {
  284. auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
  285. for (size_t i = 0; i < number_of_rx_descriptors; ++i) {
  286. auto& descriptor = rx_descriptors[i];
  287. auto region = MM.allocate_contiguous_kernel_region(8192, "E1000 RX buffer", Region::Access::Read | Region::Access::Write);
  288. VERIFY(region);
  289. m_rx_buffers_regions.append(region.release_nonnull());
  290. descriptor.addr = m_rx_buffers_regions[i].physical_page(0)->paddr().get();
  291. descriptor.status = 0;
  292. }
  293. out32(REG_RXDESCLO, m_rx_descriptors_region->physical_page(0)->paddr().get());
  294. out32(REG_RXDESCHI, 0);
  295. out32(REG_RXDESCLEN, number_of_rx_descriptors * sizeof(e1000_rx_desc));
  296. out32(REG_RXDESCHEAD, 0);
  297. out32(REG_RXDESCTAIL, number_of_rx_descriptors - 1);
  298. out32(REG_RCTRL, RCTL_EN | RCTL_SBP | RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
  299. }
  300. UNMAP_AFTER_INIT void E1000NetworkAdapter::initialize_tx_descriptors()
  301. {
  302. auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
  303. for (size_t i = 0; i < number_of_tx_descriptors; ++i) {
  304. auto& descriptor = tx_descriptors[i];
  305. auto region = MM.allocate_contiguous_kernel_region(8192, "E1000 TX buffer", Region::Access::Read | Region::Access::Write);
  306. VERIFY(region);
  307. m_tx_buffers_regions.append(region.release_nonnull());
  308. descriptor.addr = m_tx_buffers_regions[i].physical_page(0)->paddr().get();
  309. descriptor.cmd = 0;
  310. }
  311. out32(REG_TXDESCLO, m_tx_descriptors_region->physical_page(0)->paddr().get());
  312. out32(REG_TXDESCHI, 0);
  313. out32(REG_TXDESCLEN, number_of_tx_descriptors * sizeof(e1000_tx_desc));
  314. out32(REG_TXDESCHEAD, 0);
  315. out32(REG_TXDESCTAIL, 0);
  316. out32(REG_TCTRL, in32(REG_TCTRL) | TCTL_EN | TCTL_PSP);
  317. out32(REG_TIPG, 0x0060200A);
  318. }
  319. void E1000NetworkAdapter::out8(u16 address, u8 data)
  320. {
  321. dbgln_if(E1000_DEBUG, "E1000: OUT8 {:#02x} @ {:#04x}", data, address);
  322. if (m_use_mmio) {
  323. auto* ptr = (volatile u8*)(m_mmio_base.get() + address);
  324. *ptr = data;
  325. return;
  326. }
  327. m_io_base.offset(address).out(data);
  328. }
  329. void E1000NetworkAdapter::out16(u16 address, u16 data)
  330. {
  331. dbgln_if(E1000_DEBUG, "E1000: OUT16 {:#04x} @ {:#04x}", data, address);
  332. if (m_use_mmio) {
  333. auto* ptr = (volatile u16*)(m_mmio_base.get() + address);
  334. *ptr = data;
  335. return;
  336. }
  337. m_io_base.offset(address).out(data);
  338. }
  339. void E1000NetworkAdapter::out32(u16 address, u32 data)
  340. {
  341. dbgln_if(E1000_DEBUG, "E1000: OUT32 {:#08x} @ {:#04x}", data, address);
  342. if (m_use_mmio) {
  343. auto* ptr = (volatile u32*)(m_mmio_base.get() + address);
  344. *ptr = data;
  345. return;
  346. }
  347. m_io_base.offset(address).out(data);
  348. }
  349. u8 E1000NetworkAdapter::in8(u16 address)
  350. {
  351. dbgln_if(E1000_DEBUG, "E1000: IN8 @ {:#04x}", address);
  352. if (m_use_mmio)
  353. return *(volatile u8*)(m_mmio_base.get() + address);
  354. return m_io_base.offset(address).in<u8>();
  355. }
  356. u16 E1000NetworkAdapter::in16(u16 address)
  357. {
  358. dbgln_if(E1000_DEBUG, "E1000: IN16 @ {:#04x}", address);
  359. if (m_use_mmio)
  360. return *(volatile u16*)(m_mmio_base.get() + address);
  361. return m_io_base.offset(address).in<u16>();
  362. }
  363. u32 E1000NetworkAdapter::in32(u16 address)
  364. {
  365. dbgln_if(E1000_DEBUG, "E1000: IN32 @ {:#04x}", address);
  366. if (m_use_mmio)
  367. return *(volatile u32*)(m_mmio_base.get() + address);
  368. return m_io_base.offset(address).in<u32>();
  369. }
  370. void E1000NetworkAdapter::send_raw(ReadonlyBytes payload)
  371. {
  372. disable_irq();
  373. size_t tx_current = in32(REG_TXDESCTAIL) % number_of_tx_descriptors;
  374. #if E1000_DEBUG
  375. klog() << "E1000: Sending packet (" << payload.size() << " bytes)";
  376. #endif
  377. auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
  378. auto& descriptor = tx_descriptors[tx_current];
  379. VERIFY(payload.size() <= 8192);
  380. auto* vptr = (void*)m_tx_buffers_regions[tx_current].vaddr().as_ptr();
  381. memcpy(vptr, payload.data(), payload.size());
  382. descriptor.length = payload.size();
  383. descriptor.status = 0;
  384. descriptor.cmd = CMD_EOP | CMD_IFCS | CMD_RS;
  385. #if E1000_DEBUG
  386. klog() << "E1000: Using tx descriptor " << tx_current << " (head is at " << in32(REG_TXDESCHEAD) << ")";
  387. #endif
  388. tx_current = (tx_current + 1) % number_of_tx_descriptors;
  389. cli();
  390. enable_irq();
  391. out32(REG_TXDESCTAIL, tx_current);
  392. for (;;) {
  393. if (descriptor.status) {
  394. sti();
  395. break;
  396. }
  397. m_wait_queue.wait_forever("E1000NetworkAdapter");
  398. }
  399. #if E1000_DEBUG
  400. dbgln("E1000: Sent packet, status is now {:#02x}!", (u8)descriptor.status);
  401. #endif
  402. }
  403. void E1000NetworkAdapter::receive()
  404. {
  405. auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
  406. u32 rx_current;
  407. for (;;) {
  408. rx_current = in32(REG_RXDESCTAIL) % number_of_rx_descriptors;
  409. if (rx_current == (in32(REG_RXDESCHEAD) % number_of_rx_descriptors))
  410. return;
  411. rx_current = (rx_current + 1) % number_of_rx_descriptors;
  412. if (!(rx_descriptors[rx_current].status & 1))
  413. break;
  414. auto* buffer = m_rx_buffers_regions[rx_current].vaddr().as_ptr();
  415. u16 length = rx_descriptors[rx_current].length;
  416. VERIFY(length <= 8192);
  417. #if E1000_DEBUG
  418. klog() << "E1000: Received 1 packet @ " << buffer << " (" << length << ") bytes!";
  419. #endif
  420. did_receive({ buffer, length });
  421. rx_descriptors[rx_current].status = 0;
  422. out32(REG_RXDESCTAIL, rx_current);
  423. }
  424. }
  425. }