IOAPIC.cpp 11 KB

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  1. /*
  2. * Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice, this
  9. * list of conditions and the following disclaimer.
  10. *
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  19. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  22. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  24. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. */
  26. #include <Kernel/ACPI/MultiProcessorParser.h>
  27. #include <Kernel/Arch/i386/CPU.h>
  28. #include <Kernel/Interrupts/APIC.h>
  29. #include <Kernel/Interrupts/IOAPIC.h>
  30. #include <Kernel/Interrupts/InterruptManagement.h>
  31. #include <Kernel/VM/MemoryManager.h>
  32. #define IOAPIC_REDIRECTION_ENTRY_OFFSET 0x10
  33. namespace Kernel {
  34. enum DeliveryMode {
  35. Normal = 0,
  36. LowPriority = 1,
  37. SMI = 2,
  38. NMI = 3,
  39. INIT = 4,
  40. External = 7
  41. };
  42. IOAPIC::IOAPIC(ioapic_mmio_regs& regs, u32 gsi_base, Vector<RefPtr<ISAInterruptOverrideMetadata>>& isa_overrides, Vector<RefPtr<PCIInterruptOverrideMetadata>>& pci_overrides)
  43. : m_physical_access_registers(regs)
  44. , m_gsi_base(gsi_base)
  45. , m_id((read_register(0x0) >> 24) & 0xFF)
  46. , m_version(read_register(0x1) & 0xFF)
  47. , m_redirection_entries((read_register(0x1) >> 16) + 1)
  48. , m_isa_interrupt_overrides(isa_overrides)
  49. , m_pci_interrupt_overrides(pci_overrides)
  50. {
  51. klog() << "IOAPIC ID: 0x" << String::format("%x", m_id);
  52. klog() << "IOAPIC Version: 0x" << String::format("%x", m_version) << ", Redirection Entries count - " << m_redirection_entries;
  53. klog() << "IOAPIC Arbitration ID 0x" << String::format("%x", read_register(0x2));
  54. mask_all_redirection_entries();
  55. }
  56. void IOAPIC::initialize()
  57. {
  58. }
  59. void IOAPIC::map_interrupt_redirection(u8 interrupt_vector)
  60. {
  61. if (interrupt_vector == 11) {
  62. configure_redirection_entry(11, 11 + IRQ_VECTOR_BASE, DeliveryMode::LowPriority, false, true, true, true, 0);
  63. return;
  64. }
  65. for (auto redirection_override : m_isa_interrupt_overrides) {
  66. ASSERT(!redirection_override.is_null());
  67. if (redirection_override->source() != interrupt_vector)
  68. continue;
  69. bool active_low;
  70. // See ACPI spec Version 6.2, page 205 to learn more about Interrupt Overriding Flags.
  71. switch ((redirection_override->flags() & 0b11)) {
  72. case 0:
  73. active_low = false;
  74. break;
  75. case 1:
  76. active_low = false;
  77. break;
  78. case 2:
  79. ASSERT_NOT_REACHED(); // Reserved value
  80. case 3:
  81. active_low = true;
  82. break;
  83. }
  84. bool trigger_level_mode;
  85. // See ACPI spec Version 6.2, page 205 to learn more about Interrupt Overriding Flags.
  86. switch (((redirection_override->flags() >> 2) & 0b11)) {
  87. case 0:
  88. trigger_level_mode = false;
  89. break;
  90. case 1:
  91. trigger_level_mode = false;
  92. break;
  93. case 2:
  94. ASSERT_NOT_REACHED(); // Reserved value
  95. case 3:
  96. trigger_level_mode = true;
  97. break;
  98. }
  99. configure_redirection_entry(redirection_override->gsi(), redirection_override->source() + IRQ_VECTOR_BASE, DeliveryMode::LowPriority, false, active_low, trigger_level_mode, true, 0);
  100. return;
  101. }
  102. isa_identity_map(interrupt_vector);
  103. }
  104. void IOAPIC::isa_identity_map(int index)
  105. {
  106. configure_redirection_entry(index, index + IRQ_VECTOR_BASE, DeliveryMode::Normal, true, false, false, true, 1);
  107. }
  108. void IOAPIC::map_pci_interrupts()
  109. {
  110. configure_redirection_entry(11, 11 + IRQ_VECTOR_BASE, DeliveryMode::Normal, false, false, true, true, 0);
  111. }
  112. void IOAPIC::map_isa_interrupts()
  113. {
  114. InterruptDisabler disabler;
  115. for (auto redirection_override : m_isa_interrupt_overrides) {
  116. ASSERT(!redirection_override.is_null());
  117. bool active_low;
  118. // See ACPI spec Version 6.2, page 205 to learn more about Interrupt Overriding Flags.
  119. switch ((redirection_override->flags() & 0b11)) {
  120. case 0:
  121. active_low = false;
  122. break;
  123. case 1:
  124. active_low = false;
  125. break;
  126. case 2:
  127. ASSERT_NOT_REACHED();
  128. case 3:
  129. active_low = true;
  130. break;
  131. }
  132. bool trigger_level_mode;
  133. // See ACPI spec Version 6.2, page 205 to learn more about Interrupt Overriding Flags.
  134. switch (((redirection_override->flags() >> 2) & 0b11)) {
  135. case 0:
  136. trigger_level_mode = false;
  137. break;
  138. case 1:
  139. trigger_level_mode = false;
  140. break;
  141. case 2:
  142. ASSERT_NOT_REACHED();
  143. case 3:
  144. trigger_level_mode = true;
  145. break;
  146. }
  147. configure_redirection_entry(redirection_override->gsi(), redirection_override->source() + IRQ_VECTOR_BASE, 0, false, active_low, trigger_level_mode, true, 0);
  148. }
  149. }
  150. void IOAPIC::reset_all_redirection_entries() const
  151. {
  152. InterruptDisabler disabler;
  153. for (size_t index = 0; index < m_redirection_entries; index++)
  154. reset_redirection_entry(index);
  155. }
  156. void IOAPIC::hard_disable()
  157. {
  158. InterruptDisabler disabler;
  159. reset_all_redirection_entries();
  160. IRQController::hard_disable();
  161. }
  162. void IOAPIC::reset_redirection_entry(int index) const
  163. {
  164. InterruptDisabler disabler;
  165. configure_redirection_entry(index, 0, 0, false, false, false, true, 0);
  166. }
  167. void IOAPIC::configure_redirection_entry(int index, u8 interrupt_vector, u8 delivery_mode, bool logical_destination, bool active_low, bool trigger_level_mode, bool masked, u8 destination) const
  168. {
  169. ASSERT((u32)index < m_redirection_entries);
  170. u32 redirection_entry1 = interrupt_vector | (delivery_mode & 0b111) << 8 | logical_destination << 11 | active_low << 13 | trigger_level_mode << 15 | masked << 16;
  171. u32 redirection_entry2 = destination << 24;
  172. write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET, redirection_entry1);
  173. #ifdef IOAPIC_DEBUG
  174. dbg() << "IOAPIC Value: 0x" << String::format("%x", read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET));
  175. #endif
  176. write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET + 1, redirection_entry2);
  177. #ifdef IOAPIC_DEBUG
  178. dbg() << "IOAPIC Value: 0x" << String::format("%x", read_register((index << 1) + 0x11));
  179. #endif
  180. }
  181. void IOAPIC::mask_all_redirection_entries() const
  182. {
  183. InterruptDisabler disabler;
  184. for (size_t index = 0; index < m_redirection_entries; index++)
  185. mask_redirection_entry(index);
  186. }
  187. void IOAPIC::mask_redirection_entry(u8 index) const
  188. {
  189. ASSERT((u32)index < m_redirection_entries);
  190. u32 redirection_entry = read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) | (1 << 16);
  191. write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET, redirection_entry);
  192. }
  193. bool IOAPIC::is_redirection_entry_masked(u8 index) const
  194. {
  195. ASSERT((u32)index < m_redirection_entries);
  196. return (read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) & (1 << 16)) != 0;
  197. }
  198. void IOAPIC::unmask_redirection_entry(u8 index) const
  199. {
  200. ASSERT((u32)index < m_redirection_entries);
  201. u32 redirection_entry = read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET);
  202. write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET, redirection_entry & ~(1 << 16));
  203. }
  204. bool IOAPIC::is_vector_enabled(u8 interrupt_vector) const
  205. {
  206. InterruptDisabler disabler;
  207. return is_redirection_entry_masked(interrupt_vector);
  208. }
  209. u8 IOAPIC::read_redirection_entry_vector(u8 index) const
  210. {
  211. ASSERT((u32)index < m_redirection_entries);
  212. return (read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) & 0xFF);
  213. }
  214. int IOAPIC::find_redirection_entry_by_vector(u8 vector) const
  215. {
  216. InterruptDisabler disabler;
  217. for (size_t index = 0; index < m_redirection_entries; index++) {
  218. if (read_redirection_entry_vector(index) == (vector + IRQ_VECTOR_BASE))
  219. return index;
  220. }
  221. return -1;
  222. }
  223. void IOAPIC::disable(u8 interrupt_vector)
  224. {
  225. InterruptDisabler disabler;
  226. int index = find_redirection_entry_by_vector(interrupt_vector);
  227. if (index == (-1)) {
  228. map_interrupt_redirection(interrupt_vector);
  229. index = find_redirection_entry_by_vector(interrupt_vector);
  230. }
  231. ASSERT(index != (-1));
  232. mask_redirection_entry(index);
  233. }
  234. void IOAPIC::enable(u8 interrupt_vector)
  235. {
  236. InterruptDisabler disabler;
  237. int index = find_redirection_entry_by_vector(interrupt_vector);
  238. if (index == (-1)) {
  239. map_interrupt_redirection(interrupt_vector);
  240. index = find_redirection_entry_by_vector(interrupt_vector);
  241. }
  242. ASSERT(index != (-1));
  243. unmask_redirection_entry(index);
  244. }
  245. void IOAPIC::eoi(u8) const
  246. {
  247. InterruptDisabler disabler;
  248. APIC::eoi();
  249. }
  250. u16 IOAPIC::get_isr() const
  251. {
  252. InterruptDisabler disabler;
  253. ASSERT_NOT_REACHED();
  254. }
  255. u16 IOAPIC::get_irr() const
  256. {
  257. InterruptDisabler disabler;
  258. ASSERT_NOT_REACHED();
  259. }
  260. void IOAPIC::write_register(u32 index, u32 value) const
  261. {
  262. InterruptDisabler disabler;
  263. auto region = MM.allocate_kernel_region(PhysicalAddress(page_base_of(&m_physical_access_registers)), (PAGE_SIZE * 2), "IOAPIC Write", Region::Access::Read | Region::Access::Write);
  264. auto& regs = *(volatile ioapic_mmio_regs*)region->vaddr().offset(offset_in_page(&m_physical_access_registers)).as_ptr();
  265. regs.select = index;
  266. regs.window = value;
  267. #ifdef IOAPIC_DEBUG
  268. dbg() << "IOAPIC Writing, Value 0x" << String::format("%x", regs.window) << " @ offset 0x" << String::format("%x", regs.select);
  269. #endif
  270. }
  271. u32 IOAPIC::read_register(u32 index) const
  272. {
  273. InterruptDisabler disabler;
  274. auto region = MM.allocate_kernel_region(PhysicalAddress(page_base_of(&m_physical_access_registers)), (PAGE_SIZE * 2), "IOAPIC Read", Region::Access::Read | Region::Access::Write);
  275. auto& regs = *(volatile ioapic_mmio_regs*)region->vaddr().offset(offset_in_page(&m_physical_access_registers)).as_ptr();
  276. regs.select = index;
  277. #ifdef IOAPIC_DEBUG
  278. dbg() << "IOAPIC Reading, Value 0x" << String::format("%x", regs.window) << " @ offset 0x" << String::format("%x", regs.select);
  279. #endif
  280. return regs.window;
  281. }
  282. }