RTL8139NetworkAdapter.cpp 14 KB

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  1. /*
  2. * Copyright (c) 2018-2021, Andreas Kling <kling@serenityos.org>
  3. *
  4. * SPDX-License-Identifier: BSD-2-Clause
  5. */
  6. #include <AK/MACAddress.h>
  7. #include <Kernel/Bus/PCI/API.h>
  8. #include <Kernel/Debug.h>
  9. #include <Kernel/Net/NetworkingManagement.h>
  10. #include <Kernel/Net/Realtek/RTL8139NetworkAdapter.h>
  11. #include <Kernel/Sections.h>
  12. namespace Kernel {
  13. #define REG_MAC 0x00
  14. #define REG_MAR0 0x08
  15. #define REG_MAR4 0x12
  16. #define REG_TXSTATUS0 0x10
  17. #define REG_TXADDR0 0x20
  18. #define REG_RXBUF 0x30
  19. #define REG_COMMAND 0x37
  20. #define REG_CAPR 0x38
  21. #define REG_IMR 0x3C
  22. #define REG_ISR 0x3E
  23. #define REG_TXCFG 0x40
  24. #define REG_RXCFG 0x44
  25. #define REG_MPC 0x4C
  26. #define REG_CFG9346 0x50
  27. #define REG_CONFIG1 0x52
  28. #define REG_MSR 0x58
  29. #define REG_BMCR 0x62
  30. #define REG_ANLPAR 0x68
  31. #define TX_STATUS_OWN 0x2000
  32. #define TX_STATUS_THRESHOLD_MAX 0x3F0000
  33. #define COMMAND_RX_EMPTY 0x01
  34. #define COMMAND_TX_ENABLE 0x04
  35. #define COMMAND_RX_ENABLE 0x08
  36. #define COMMAND_RESET 0x10
  37. #define INT_RXOK 0x01
  38. #define INT_RXERR 0x02
  39. #define INT_TXOK 0x04
  40. #define INT_TXERR 0x08
  41. #define INT_RX_BUFFER_OVERFLOW 0x10
  42. #define INT_LINK_CHANGE 0x20
  43. #define INT_RX_FIFO_OVERFLOW 0x40
  44. #define INT_LENGTH_CHANGE 0x2000
  45. #define INT_SYSTEM_ERROR 0x8000
  46. #define CFG9346_NONE 0x00
  47. #define CFG9346_EEM0 0x40
  48. #define CFG9346_EEM1 0x80
  49. #define TXCFG_TXRR_ZERO 0x00
  50. #define TXCFG_MAX_DMA_16B 0x000
  51. #define TXCFG_MAX_DMA_32B 0x100
  52. #define TXCFG_MAX_DMA_64B 0x200
  53. #define TXCFG_MAX_DMA_128B 0x300
  54. #define TXCFG_MAX_DMA_256B 0x400
  55. #define TXCFG_MAX_DMA_512B 0x500
  56. #define TXCFG_MAX_DMA_1K 0x600
  57. #define TXCFG_MAX_DMA_2K 0x700
  58. #define TXCFG_IFG11 0x3000000
  59. #define RXCFG_AAP 0x01
  60. #define RXCFG_APM 0x02
  61. #define RXCFG_AM 0x04
  62. #define RXCFG_AB 0x08
  63. #define RXCFG_AR 0x10
  64. #define RXCFG_WRAP_INHIBIT 0x80
  65. #define RXCFG_MAX_DMA_16B 0x000
  66. #define RXCFG_MAX_DMA_32B 0x100
  67. #define RXCFG_MAX_DMA_64B 0x200
  68. #define RXCFG_MAX_DMA_128B 0x300
  69. #define RXCFG_MAX_DMA_256B 0x400
  70. #define RXCFG_MAX_DMA_512B 0x500
  71. #define RXCFG_MAX_DMA_1K 0x600
  72. #define RXCFG_MAX_DMA_UNLIMITED 0x0700
  73. #define RXCFG_RBLN_8K 0x0000
  74. #define RXCFG_RBLN_16K 0x0800
  75. #define RXCFG_RBLN_32K 0x1000
  76. #define RXCFG_RBLN_64K 0x1800
  77. #define RXCFG_FTH_NONE 0xE000
  78. #define MSR_LINKB 0x02
  79. #define MSR_SPEED_10 0x08
  80. #define MSR_RX_FLOW_CONTROL_ENABLE 0x40
  81. #define BMCR_SPEED 0x2000
  82. #define BMCR_AUTO_NEGOTIATE 0x1000
  83. #define BMCR_DUPLEX 0x0100
  84. #define ANLPAR_10FD 0x0040
  85. #define ANLPAR_TXFD 0x0100
  86. #define RX_MULTICAST 0x8000
  87. #define RX_PHYSICAL_MATCH 0x4000
  88. #define RX_BROADCAST 0x2000
  89. #define RX_INVALID_SYMBOL_ERROR 0x20
  90. #define RX_RUNT 0x10
  91. #define RX_LONG 0x08
  92. #define RX_CRC_ERROR 0x04
  93. #define RX_FRAME_ALIGNMENT_ERROR 0x02
  94. #define RX_OK 0x01
  95. #define PACKET_SIZE_MAX 0x600
  96. #define PACKET_SIZE_MIN 0x16
  97. #define RX_BUFFER_SIZE 32768
  98. #define TX_BUFFER_SIZE PACKET_SIZE_MAX
  99. UNMAP_AFTER_INIT LockRefPtr<RTL8139NetworkAdapter> RTL8139NetworkAdapter::try_to_initialize(PCI::DeviceIdentifier const& pci_device_identifier)
  100. {
  101. constexpr PCI::HardwareID rtl8139_id = { 0x10EC, 0x8139 };
  102. if (pci_device_identifier.hardware_id() != rtl8139_id)
  103. return {};
  104. u8 irq = pci_device_identifier.interrupt_line().value();
  105. // FIXME: Better propagate errors here
  106. auto interface_name_or_error = NetworkingManagement::generate_interface_name_from_pci_address(pci_device_identifier);
  107. if (interface_name_or_error.is_error())
  108. return {};
  109. auto registers_io_window = MUST(IOWindow::create_for_pci_device_bar(pci_device_identifier, PCI::HeaderType0BaseRegister::BAR0));
  110. return adopt_lock_ref_if_nonnull(new (nothrow) RTL8139NetworkAdapter(pci_device_identifier.address(), irq, move(registers_io_window), interface_name_or_error.release_value()));
  111. }
  112. UNMAP_AFTER_INIT RTL8139NetworkAdapter::RTL8139NetworkAdapter(PCI::Address address, u8 irq, NonnullOwnPtr<IOWindow> registers_io_window, NonnullOwnPtr<KString> interface_name)
  113. : NetworkAdapter(move(interface_name))
  114. , PCI::Device(address)
  115. , IRQHandler(irq)
  116. , m_registers_io_window(move(registers_io_window))
  117. , m_rx_buffer(MM.allocate_contiguous_kernel_region(Memory::page_round_up(RX_BUFFER_SIZE + PACKET_SIZE_MAX).release_value_but_fixme_should_propagate_errors(), "RTL8139 RX"sv, Memory::Region::Access::ReadWrite).release_value())
  118. , m_packet_buffer(MM.allocate_contiguous_kernel_region(Memory::page_round_up(PACKET_SIZE_MAX).release_value_but_fixme_should_propagate_errors(), "RTL8139 Packet buffer"sv, Memory::Region::Access::ReadWrite).release_value())
  119. {
  120. m_tx_buffers.ensure_capacity(RTL8139_TX_BUFFER_COUNT);
  121. dmesgln("RTL8139: Found @ {}", pci_address());
  122. enable_bus_mastering(pci_address());
  123. dmesgln("RTL8139: I/O port base: {}", m_registers_io_window);
  124. dmesgln("RTL8139: Interrupt line: {}", interrupt_number());
  125. // we add space to account for overhang from the last packet - the rtl8139
  126. // can optionally guarantee that packets will be contiguous by
  127. // purposefully overrunning the rx buffer
  128. dbgln("RTL8139: RX buffer: {}", m_rx_buffer->physical_page(0)->paddr());
  129. for (int i = 0; i < RTL8139_TX_BUFFER_COUNT; i++) {
  130. m_tx_buffers.append(MM.allocate_contiguous_kernel_region(Memory::page_round_up(TX_BUFFER_SIZE).release_value_but_fixme_should_propagate_errors(), "RTL8139 TX"sv, Memory::Region::Access::Write | Memory::Region::Access::Read).release_value());
  131. dbgln("RTL8139: TX buffer {}: {}", i, m_tx_buffers[i]->physical_page(0)->paddr());
  132. }
  133. reset();
  134. read_mac_address();
  135. auto const& mac = mac_address();
  136. dmesgln("RTL8139: MAC address: {}", mac.to_string());
  137. enable_irq();
  138. }
  139. UNMAP_AFTER_INIT RTL8139NetworkAdapter::~RTL8139NetworkAdapter() = default;
  140. bool RTL8139NetworkAdapter::handle_irq(RegisterState const&)
  141. {
  142. bool was_handled = false;
  143. for (;;) {
  144. int status = in16(REG_ISR);
  145. out16(REG_ISR, status);
  146. m_entropy_source.add_random_event(status);
  147. dbgln_if(RTL8139_DEBUG, "RTL8139: handle_irq status={:#04x}", status);
  148. if ((status & (INT_RXOK | INT_RXERR | INT_TXOK | INT_TXERR | INT_RX_BUFFER_OVERFLOW | INT_LINK_CHANGE | INT_RX_FIFO_OVERFLOW | INT_LENGTH_CHANGE | INT_SYSTEM_ERROR)) == 0)
  149. break;
  150. was_handled = true;
  151. if (status & INT_RXOK) {
  152. dbgln_if(RTL8139_DEBUG, "RTL8139: RX ready");
  153. receive();
  154. }
  155. if (status & INT_RXERR) {
  156. dmesgln("RTL8139: RX error - resetting device");
  157. reset();
  158. }
  159. if (status & INT_TXOK) {
  160. dbgln_if(RTL8139_DEBUG, "RTL8139: TX complete");
  161. }
  162. if (status & INT_TXERR) {
  163. dmesgln("RTL8139: TX error - resetting device");
  164. reset();
  165. }
  166. if (status & INT_RX_BUFFER_OVERFLOW) {
  167. dmesgln("RTL8139: RX buffer overflow");
  168. }
  169. if (status & INT_LINK_CHANGE) {
  170. m_link_up = (in8(REG_MSR) & MSR_LINKB) == 0;
  171. dmesgln("RTL8139: Link status changed up={}", m_link_up);
  172. }
  173. if (status & INT_RX_FIFO_OVERFLOW) {
  174. dmesgln("RTL8139: RX FIFO overflow");
  175. }
  176. if (status & INT_LENGTH_CHANGE) {
  177. dmesgln("RTL8139: Cable length change");
  178. }
  179. if (status & INT_SYSTEM_ERROR) {
  180. dmesgln("RTL8139: System error - resetting device");
  181. reset();
  182. }
  183. }
  184. return was_handled;
  185. }
  186. void RTL8139NetworkAdapter::reset()
  187. {
  188. m_rx_buffer_offset = 0;
  189. m_tx_next_buffer = 0;
  190. // reset the device to clear out all the buffers and config
  191. out8(REG_COMMAND, COMMAND_RESET);
  192. while ((in8(REG_COMMAND) & COMMAND_RESET) != 0)
  193. ;
  194. // unlock config registers
  195. out8(REG_CFG9346, CFG9346_EEM0 | CFG9346_EEM1);
  196. // turn on multicast
  197. out32(REG_MAR0, 0xffffffff);
  198. out32(REG_MAR4, 0xffffffff);
  199. // enable rx/tx
  200. out8(REG_COMMAND, COMMAND_RX_ENABLE | COMMAND_TX_ENABLE);
  201. // device might be in sleep mode, this will take it out
  202. out8(REG_CONFIG1, 0);
  203. // set up rx buffer
  204. out32(REG_RXBUF, m_rx_buffer->physical_page(0)->paddr().get());
  205. // reset missed packet counter
  206. out8(REG_MPC, 0);
  207. // "basic mode control register" options - 100mbit, full duplex, auto
  208. // negotiation
  209. out16(REG_BMCR, BMCR_SPEED | BMCR_AUTO_NEGOTIATE | BMCR_DUPLEX);
  210. // enable flow control
  211. out8(REG_MSR, MSR_RX_FLOW_CONTROL_ENABLE);
  212. // configure rx: accept physical (MAC) match, multicast, and broadcast,
  213. // use the optional contiguous packet feature, the maximum dma transfer
  214. // size, a 32k buffer, and no fifo threshold
  215. out32(REG_RXCFG, RXCFG_APM | RXCFG_AM | RXCFG_AB | RXCFG_WRAP_INHIBIT | RXCFG_MAX_DMA_UNLIMITED | RXCFG_RBLN_32K | RXCFG_FTH_NONE);
  216. // configure tx: default retry count (16), max DMA burst size of 1024
  217. // bytes, interframe gap time of the only allowable value. the DMA burst
  218. // size is important - silent failures have been observed with 2048 bytes.
  219. out32(REG_TXCFG, TXCFG_TXRR_ZERO | TXCFG_MAX_DMA_1K | TXCFG_IFG11);
  220. // tell the chip where we want it to DMA from for outgoing packets.
  221. for (int i = 0; i < 4; i++)
  222. out32(REG_TXADDR0 + (i * 4), m_tx_buffers[i]->physical_page(0)->paddr().get());
  223. // re-lock config registers
  224. out8(REG_CFG9346, CFG9346_NONE);
  225. // enable rx/tx again in case they got turned off (apparently some cards
  226. // do this?)
  227. out8(REG_COMMAND, COMMAND_RX_ENABLE | COMMAND_TX_ENABLE);
  228. // choose irqs, then clear any pending
  229. out16(REG_IMR, INT_RXOK | INT_RXERR | INT_TXOK | INT_TXERR | INT_RX_BUFFER_OVERFLOW | INT_LINK_CHANGE | INT_RX_FIFO_OVERFLOW | INT_LENGTH_CHANGE | INT_SYSTEM_ERROR);
  230. out16(REG_ISR, 0xffff);
  231. // Set the initial link up status.
  232. m_link_up = (in8(REG_MSR) & MSR_LINKB) == 0;
  233. }
  234. UNMAP_AFTER_INIT void RTL8139NetworkAdapter::read_mac_address()
  235. {
  236. MACAddress mac {};
  237. for (int i = 0; i < 6; i++)
  238. mac[i] = in8(REG_MAC + i);
  239. set_mac_address(mac);
  240. }
  241. void RTL8139NetworkAdapter::send_raw(ReadonlyBytes payload)
  242. {
  243. dbgln_if(RTL8139_DEBUG, "RTL8139: send_raw length={}", payload.size());
  244. if (payload.size() > PACKET_SIZE_MAX) {
  245. dmesgln("RTL8139: Packet was too big; discarding");
  246. return;
  247. }
  248. int hw_buffer = -1;
  249. for (int i = 0; i < RTL8139_TX_BUFFER_COUNT; i++) {
  250. int potential_buffer = (m_tx_next_buffer + i) % 4;
  251. auto status = in32(REG_TXSTATUS0 + (potential_buffer * 4));
  252. if (status & TX_STATUS_OWN) {
  253. hw_buffer = potential_buffer;
  254. break;
  255. }
  256. }
  257. if (hw_buffer == -1) {
  258. dmesgln("RTL8139: Hardware buffers full; discarding packet");
  259. return;
  260. }
  261. dbgln_if(RTL8139_DEBUG, "RTL8139: Chose buffer {}", hw_buffer);
  262. m_tx_next_buffer = (hw_buffer + 1) % 4;
  263. memcpy(m_tx_buffers[hw_buffer]->vaddr().as_ptr(), payload.data(), payload.size());
  264. memset(m_tx_buffers[hw_buffer]->vaddr().as_ptr() + payload.size(), 0, TX_BUFFER_SIZE - payload.size());
  265. // the rtl8139 will not actually emit packets onto the network if they're
  266. // smaller than 64 bytes. the rtl8139 adds a checksum to the end of each
  267. // packet, and that checksum is four bytes long, so we pad the packet to
  268. // 60 bytes if necessary to make sure the whole thing is large enough.
  269. auto length = payload.size();
  270. if (length < 60) {
  271. dbgln_if(RTL8139_DEBUG, "RTL8139: adjusting payload size from {} to 60", length);
  272. length = 60;
  273. }
  274. out32(REG_TXSTATUS0 + (hw_buffer * 4), length);
  275. }
  276. void RTL8139NetworkAdapter::receive()
  277. {
  278. auto* start_of_packet = m_rx_buffer->vaddr().as_ptr() + m_rx_buffer_offset;
  279. u16 status = *(u16 const*)(start_of_packet + 0);
  280. u16 length = *(u16 const*)(start_of_packet + 2);
  281. dbgln_if(RTL8139_DEBUG, "RTL8139: receive, status={:#04x}, length={}, offset={}", status, length, m_rx_buffer_offset);
  282. if (!(status & RX_OK) || (status & (RX_INVALID_SYMBOL_ERROR | RX_CRC_ERROR | RX_FRAME_ALIGNMENT_ERROR)) || (length >= PACKET_SIZE_MAX) || (length < PACKET_SIZE_MIN)) {
  283. dmesgln("RTL8139: receive got bad packet, status={:#04x}, length={}", status, length);
  284. reset();
  285. return;
  286. }
  287. // we never have to worry about the packet wrapping around the buffer,
  288. // since we set RXCFG_WRAP_INHIBIT, which allows the rtl8139 to write data
  289. // past the end of the allotted space.
  290. memcpy(m_packet_buffer->vaddr().as_ptr(), (u8 const*)(start_of_packet + 4), length - 4);
  291. // let the card know that we've read this data
  292. m_rx_buffer_offset = ((m_rx_buffer_offset + length + 4 + 3) & ~3) % RX_BUFFER_SIZE;
  293. out16(REG_CAPR, m_rx_buffer_offset - 0x10);
  294. m_rx_buffer_offset %= RX_BUFFER_SIZE;
  295. did_receive({ m_packet_buffer->vaddr().as_ptr(), (size_t)(length - 4) });
  296. }
  297. void RTL8139NetworkAdapter::out8(u16 address, u8 data)
  298. {
  299. m_registers_io_window->write8(address, data);
  300. }
  301. void RTL8139NetworkAdapter::out16(u16 address, u16 data)
  302. {
  303. m_registers_io_window->write16(address, data);
  304. }
  305. void RTL8139NetworkAdapter::out32(u16 address, u32 data)
  306. {
  307. m_registers_io_window->write32(address, data);
  308. }
  309. u8 RTL8139NetworkAdapter::in8(u16 address)
  310. {
  311. return m_registers_io_window->read8(address);
  312. }
  313. u16 RTL8139NetworkAdapter::in16(u16 address)
  314. {
  315. return m_registers_io_window->read16(address);
  316. }
  317. u32 RTL8139NetworkAdapter::in32(u16 address)
  318. {
  319. return m_registers_io_window->read32(address);
  320. }
  321. bool RTL8139NetworkAdapter::link_full_duplex()
  322. {
  323. // Note: this code assumes auto-negotiation is enabled (which is now always the case) and
  324. // bases the duplex state on the link partner advertisement.
  325. // If non-auto-negotiation is ever implemented this should be changed.
  326. u16 anlpar = in16(REG_ANLPAR);
  327. return !!(anlpar & (ANLPAR_TXFD | ANLPAR_10FD));
  328. }
  329. i32 RTL8139NetworkAdapter::link_speed()
  330. {
  331. if (!link_up())
  332. return NetworkAdapter::LINKSPEED_INVALID;
  333. u16 msr = in16(REG_MSR);
  334. return msr & MSR_SPEED_10 ? 10 : 100;
  335. }
  336. }