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9 commits

Author SHA1 Message Date
Liav A
9e66eb160c Kernel: Add the new APIC namespace 
Also, the enable() function is now correct and will use the right
registers and values. In addition to that, write_register() and
read_registers() are not relying on identity mapping anymore.
 2020-02-24 11:27:03 +01:00
Liav A
12dbb7ca49 Kernel: Add MSIHandler class 
This is a stub for now, since we don't support Message Signaled
Interrupts yet.
 2020-02-24 11:27:03 +01:00
Liav A
9d281b4b15 Kernel: Add UnhandledInterruptHandler class 
This class will be used to represent an IRQ vector handler that wasn't
assigned to any IRQ Handler.
 2020-02-24 11:27:03 +01:00
Liav A
9587f2d3ee Kernel: Add SharedIRQHandler class 
This class represents a shared interrupt handler. This class will not be
created automatically but only if two IRQ Handlers are sharing the same
IRQ number.
 2020-02-24 11:27:03 +01:00
Liav A
dd7522bdb2 Kernel: Add new IRQHandler class 
This class will replace the old IRQHandler class later.
 2020-02-24 11:27:03 +01:00
Liav A
b201b23363 Kernel: Add Interrupt Management and Generic Interrupt Handler 
The GenericInterruptHandler class will be used to represent
an abstract interrupt handler. The InterruptManagement class will
represent a centralized component to manage interrupts.
 2020-02-24 11:27:03 +01:00
Liav A
e760ebcacb Kernel: Add the IOAPIC class 
This class inherits from IRQController class, and represents
the 82093AA IOAPIC chip.
 2020-02-24 11:27:03 +01:00
Liav A
7d59a67504 Kernel: Add the PIC class 
This class inherits from IRQController class, and represents
the common Intel 8259 PIC chip.
 2020-02-24 11:27:03 +01:00
Liav A
b56afbea17 Kernel: Add IRQController class 
This class is an abstraction layer for different IRQ controllers
that are present in a typical system.
 2020-02-24 11:27:03 +01:00