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Author	SHA1	Message	Date
Liav A	68c3f9aa5a	Kernel/Interrupts: Move PCIIRQHandler => PCI::IRQHandler This class is part of the PCI code so let's move it to the PCI namespace like other handling code parts of the PCI bus.	2023-09-16 14:04:17 -06:00
Pankaj Raghav	d14c2a3583	Kernel: Move handle_interrupt out-of-line in PCIIRQHandler Upgrade to GCC 13.1.0 triggered an UBSAN in PCIIRQHandler. Moving the handle_interrupt() function out-of-line fixes this issue.	2023-05-21 18:01:29 -06:00
Pankaj Raghav	feb48cbc7c	Kernel: Introduce PCIIRQHandler PCIIRQHandler is a generic IRQ handler that the device driver can inherit to use either Pin or MSI(x) based interrupt mechanism. The PCIIRQHandler can do what the existing IRQHandler can do for pin based interrupts but also deal with MSI based interrupts. We can hopefully convert all the PCI based devices to use this handler so that MSI(x) can be used.	2023-05-07 21:16:41 +02:00

Author

SHA1

Message

Date

Liav A

68c3f9aa5a

Kernel/Interrupts: Move PCIIRQHandler => PCI::IRQHandler

This class is part of the PCI code so let's move it to the PCI namespace
like other handling code parts of the PCI bus.

2023-09-16 14:04:17 -06:00

Pankaj Raghav

d14c2a3583

Kernel: Move handle_interrupt out-of-line in PCIIRQHandler

Upgrade to GCC 13.1.0 triggered an UBSAN in PCIIRQHandler. Moving the
handle_interrupt() function out-of-line fixes this issue.

2023-05-21 18:01:29 -06:00

Pankaj Raghav

feb48cbc7c

Kernel: Introduce PCIIRQHandler

PCIIRQHandler is a generic IRQ handler that the device driver can
inherit to use either Pin or MSI(x) based interrupt mechanism.

The PCIIRQHandler can do what the existing IRQHandler can do for pin
based interrupts but also deal with MSI based interrupts. We can
hopefully convert all the PCI based devices to use this handler so that
MSI(x) can be used.

2023-05-07 21:16:41 +02:00

3 commits