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Kernel/aarch64: Properly initialize T0SZ and T1SZ fields in TCR_EL1

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By default these 2 fields were zero, which made it rely on
implementation defined behavior whether these fields internally would be
set to the correct value. The ARM processor in the Raspberry PI (and
QEMU 6.x) would actually fixup these values, whereas QEMU 7.x now does
not do that anymore, and a translation fault would be generated instead.

For more context see the relevant QEMU issue:
 - https://gitlab.com/qemu-project/qemu/-/issues/1157

Fixes #14856
This commit is contained in:
Timon Kruiper 2022-08-19 19:11:06 +02:00 committed by Tim Flynn
parent 987927a596
commit d62bd3c635
Notes: sideshowbarker 2024-07-17 07:52:37 +09:00 
Author: https://github.com/FireFox317
Commit: https://github.com/SerenityOS/serenity/commit/d62bd3c635
Pull-request: https://github.com/SerenityOS/serenity/pull/14925
Issue: https://github.com/SerenityOS/serenity/issues/14856
Reviewed-by: https://github.com/nico ✅
1 changed files with 2 additions and 0 deletions
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2
Kernel/Arch/aarch64/MMU.cpp
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@ -164,10 +164,12 @@ static void activate_mmu()
tcr_el1.SH1 = Aarch64::TCR_EL1::InnerShareable;
tcr_el1.ORGN1 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN1 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.T1SZ = 16;
tcr_el1.SH0 = Aarch64::TCR_EL1::InnerShareable;
tcr_el1.ORGN0 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN0 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.T0SZ = 16;
tcr_el1.TG1 = Aarch64::TCR_EL1::TG1GranuleSize::Size_4KB;
tcr_el1.TG0 = Aarch64::TCR_EL1::TG0GranuleSize::Size_4KB;