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@@ -51,6 +51,34 @@ void SoftCPU::dump() const
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printf("o=%u s=%u z=%u a=%u p=%u c=%u\n", m_of, m_sf, m_zf, m_af, m_pf, m_cf);
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printf("o=%u s=%u z=%u a=%u p=%u c=%u\n", m_of, m_sf, m_zf, m_af, m_pf, m_cf);
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}
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}
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+u32 SoftCPU::read_memory32(X86::LogicalAddress address)
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+{
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+ ASSERT(address.selector() == 0x20);
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+ auto value = m_emulator.mmu().read32(address.offset());
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+ printf("\033[36;1mread_memory32: @%08x -> %08x\033[0m\n", address.offset(), value);
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+ return value;
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+}
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+
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+void SoftCPU::write_memory32(X86::LogicalAddress address, u32 value)
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+{
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+ ASSERT(address.selector() == 0x20);
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+ printf("\033[35;1mwrite_memory32: @%08x <- %08x\033[0m\n", address.offset(), value);
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+ m_emulator.mmu().write32(address.offset(), value);
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+}
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+
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+void SoftCPU::push32(u32 value)
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+{
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+ m_esp -= sizeof(value);
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+ write_memory32({ get_ss(), get_esp() }, value);
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+}
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+
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+u32 SoftCPU::pop32()
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+{
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+ auto value = read_memory32({ get_ss(), get_esp() });
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+ m_esp += sizeof(value);
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+ return value;
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+}
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+
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void SoftCPU::AAA(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAA(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAD(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAD(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAM(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAM(const X86::Instruction&) { TODO(); }
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@@ -346,7 +374,12 @@ void SoftCPU::POP_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::POP_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::POP_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::POP_SS(const X86::Instruction&) { TODO(); }
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void SoftCPU::POP_SS(const X86::Instruction&) { TODO(); }
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void SoftCPU::POP_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::POP_reg16(const X86::Instruction&) { TODO(); }
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-void SoftCPU::POP_reg32(const X86::Instruction&) { TODO(); }
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+
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+void SoftCPU::POP_reg32(const X86::Instruction& insn)
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+{
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+ *m_reg32_table[insn.register_index()] = pop32();
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+}
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+
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void SoftCPU::PUSHA(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSHA(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSHAD(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSHAD(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSHF(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSHF(const X86::Instruction&) { TODO(); }
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@@ -364,7 +397,12 @@ void SoftCPU::PUSH_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSH_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSH_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSH_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSH_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSH_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSH_reg16(const X86::Instruction&) { TODO(); }
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-void SoftCPU::PUSH_reg32(const X86::Instruction&) { TODO(); }
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+
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+void SoftCPU::PUSH_reg32(const X86::Instruction& insn)
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+{
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+ push32(*m_reg32_table[insn.register_index()]);
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+}
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+
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void SoftCPU::RCL_RM16_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM16_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::RCL_RM16_imm8(const X86::Instruction&) { TODO(); }
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