UserspaceEmulator: Start building a userspace X86 emulator :^)
This introduces a new X86 CPU emulator for running SerenityOS userspace programs in a virtualized interpreter environment. The main goal is to be able to instrument memory accesses and catch interesting bugs that are very hard to find otherwise. But before we can do fancy things like that, we have to build a competent emulator able to actually run programs. This initial version is able to run a very small program that makes some tiny syscalls, but nothing more.
This commit is contained in:
Andreas Kling
parent
6440e59ead
commit
8d8bb07476
Notes:
sideshowbarker
2024-07-19 05:01:49 +09:00
Author: https://github.com/awesomekling Commit: https://github.com/SerenityOS/serenity/commit/8d8bb07476d
8 changed files with 1279 additions and 0 deletions
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@ -27,5 +27,6 @@ alias pv=Profiler
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alias ws=WebServer
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alias sl=Solitaire
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alias wv=WebView
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alias ue=UserspaceEmulator
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alias ll='ls -l'
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@ -1,4 +1,5 @@
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add_subdirectory(HackStudio)
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add_subdirectory(Inspector)
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add_subdirectory(Profiler)
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add_subdirectory(UserspaceEmulator)
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add_subdirectory(VisualBuilder)
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8
DevTools/UserspaceEmulator/CMakeLists.txt
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8
DevTools/UserspaceEmulator/CMakeLists.txt
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@ -0,0 +1,8 @@
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set(SOURCES
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SoftCPU.cpp
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Emulator.cpp
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main.cpp
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)
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serenity_bin(UserspaceEmulator)
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target_link_libraries(UserspaceEmulator LibX86 LibCore)
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89
DevTools/UserspaceEmulator/Emulator.cpp
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89
DevTools/UserspaceEmulator/Emulator.cpp
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@ -0,0 +1,89 @@
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/*
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* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "Emulator.h"
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#include "SoftCPU.h"
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#include <AK/LogStream.h>
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#include <Kernel/API/Syscall.h>
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#include <unistd.h>
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#include <stdio.h>
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namespace UserspaceEmulator {
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Emulator::Emulator()
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: m_cpu(*this)
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{
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}
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int Emulator::exec(X86::SimpleInstructionStream& stream, u32 base)
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{
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size_t offset = 0;
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while (!m_shutdown) {
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auto insn = X86::Instruction::from_stream(stream, true, true);
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out() << "instruction: " << insn.to_string(base + offset);
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(m_cpu.*insn.handler())(insn);
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m_cpu.dump();
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offset += insn.length();
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if (insn.mnemonic() == "RET")
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break;
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}
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return m_exit_status;
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}
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u32 Emulator::virt_syscall(u32 function, u32 arg1, u32 arg2, u32 arg3)
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{
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(void) arg2;
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(void) arg3;
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printf("Syscall: %s (%x)\n", Syscall::to_string((Syscall::Function)function), function);
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switch (function) {
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case SC_getuid:
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return virt$getuid();
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case SC_exit:
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virt$exit((int)arg1);
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return 0;
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default:
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warn() << "Unimplemented syscall!";
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TODO();
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}
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}
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uid_t Emulator::virt$getuid()
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{
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return getuid();
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}
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void Emulator::virt$exit(int status)
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{
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out() << "exit(" << status << "), shutting down!";
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m_exit_status = status;
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m_shutdown = true;
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}
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}
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53
DevTools/UserspaceEmulator/Emulator.h
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53
DevTools/UserspaceEmulator/Emulator.h
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#include "SoftCPU.h"
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#include <AK/Types.h>
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#include <LibX86/Instruction.h>
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#include <sys/types.h>
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namespace UserspaceEmulator {
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class Emulator {
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public:
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Emulator();
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int exec(X86::SimpleInstructionStream&, u32 base);
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u32 virt_syscall(u32 function, u32 arg1, u32 arg2, u32 arg3);
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private:
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SoftCPU m_cpu;
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uid_t virt$getuid();
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void virt$exit(int);
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bool m_shutdown { false };
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int m_exit_status { 0 };
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};
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}
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540
DevTools/UserspaceEmulator/SoftCPU.cpp
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540
DevTools/UserspaceEmulator/SoftCPU.cpp
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@ -0,0 +1,540 @@
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/*
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* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "SoftCPU.h"
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#include "Emulator.h"
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#include <AK/Assertions.h>
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#include <stdio.h>
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namespace UserspaceEmulator {
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SoftCPU::SoftCPU(Emulator& emulator)
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: m_emulator(emulator)
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{
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m_reg32_table[X86::RegisterEAX] = &m_eax;
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m_reg32_table[X86::RegisterEBX] = &m_ebx;
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m_reg32_table[X86::RegisterECX] = &m_ecx;
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m_reg32_table[X86::RegisterEDX] = &m_edx;
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m_reg32_table[X86::RegisterEBP] = &m_ebp;
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m_reg32_table[X86::RegisterESP] = &m_esp;
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m_reg32_table[X86::RegisterESI] = &m_esi;
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m_reg32_table[X86::RegisterEDI] = &m_edi;
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}
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void SoftCPU::dump() const
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{
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printf("eax: %08x ebx: %08x ecx: %08x edx: %08x\n", m_eax, m_ebx, m_ecx, m_edx);
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printf("ebp: %08x esp: %08x esi: %08x edi: %08x\n", m_ebp, m_esp, m_esi, m_edi);
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}
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void SoftCPU::AAA(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAD(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAM(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAS(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_AL_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_AX_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_EAX_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_RM16_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_RM32_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_RM8_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_RM8_reg8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADC_reg8_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_AL_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_AX_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_EAX_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_RM16_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_RM32_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_RM8_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_RM8_reg8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ADD_reg8_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_AL_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_AX_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_EAX_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_RM16_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_RM32_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_RM8_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_RM8_reg8(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::AND_reg8_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ARPL(const X86::Instruction&) { TODO(); }
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void SoftCPU::BOUND(const X86::Instruction&) { TODO(); }
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void SoftCPU::BSF_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::BSF_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::BSR_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::BSR_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::BSWAP_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTC_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTC_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTC_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTC_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTR_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTR_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTR_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTR_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTS_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTS_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTS_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::BTS_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::BT_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::BT_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::BT_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::BT_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CALL_FAR_mem16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CALL_FAR_mem32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CALL_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CALL_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CALL_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CALL_imm16_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CALL_imm16_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CALL_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CBW(const X86::Instruction&) { TODO(); }
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void SoftCPU::CDQ(const X86::Instruction&) { TODO(); }
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void SoftCPU::CLC(const X86::Instruction&) { TODO(); }
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void SoftCPU::CLD(const X86::Instruction&) { TODO(); }
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void SoftCPU::CLI(const X86::Instruction&) { TODO(); }
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void SoftCPU::CLTS(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMC(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMOVcc_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMOVcc_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMPSB(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMPSD(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMPSW(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMPXCHG_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMPXCHG_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMPXCHG_RM8_reg8(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_AL_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_AX_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_EAX_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_RM16_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_RM32_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_RM8_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_RM8_reg8(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::CMP_reg8_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::CPUID(const X86::Instruction&) { TODO(); }
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void SoftCPU::CWD(const X86::Instruction&) { TODO(); }
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void SoftCPU::CWDE(const X86::Instruction&) { TODO(); }
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void SoftCPU::DAA(const X86::Instruction&) { TODO(); }
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void SoftCPU::DAS(const X86::Instruction&) { TODO(); }
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void SoftCPU::DEC_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::DEC_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::DEC_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::DEC_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::DEC_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::DIV_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::DIV_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::DIV_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::ENTER16(const X86::Instruction&) { TODO(); }
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void SoftCPU::ENTER32(const X86::Instruction&) { TODO(); }
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void SoftCPU::ESCAPE(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::HLT(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IDIV_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IDIV_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IDIV_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_reg16_RM16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_reg16_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_reg32_RM32_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IMUL_reg32_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INC_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INC_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INC_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INC_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INC_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INSB(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INSD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INSW(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INT3(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::INTO(const X86::Instruction&) { TODO(); }
|
||||
|
||||
void SoftCPU::INT_imm8(const X86::Instruction& insn)
|
||||
{
|
||||
ASSERT(insn.imm8() == 0x82);
|
||||
m_eax = m_emulator.virt_syscall(m_eax, m_edx, m_ecx, m_ebx);
|
||||
}
|
||||
|
||||
void SoftCPU::INVLPG(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IN_AL_DX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IN_AL_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IN_AX_DX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IN_AX_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IN_EAX_DX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IN_EAX_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::IRET(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JCXZ_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_FAR_mem16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_FAR_mem32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_imm16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_imm16_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::JMP_short_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::Jcc_NEAR_imm(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::Jcc_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LAHF(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LAR_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LAR_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LDS_reg16_mem16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LDS_reg32_mem32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LEAVE16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LEAVE32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LEA_reg16_mem16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LEA_reg32_mem32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LES_reg16_mem16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LES_reg32_mem32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LFS_reg16_mem16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LFS_reg32_mem32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LGDT(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LGS_reg16_mem16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LGS_reg32_mem32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LIDT(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LLDT_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LMSW_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LODSB(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LODSD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LODSW(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LOOPNZ_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LOOPZ_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LOOP_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LSL_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LSL_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LSS_reg16_mem16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LSS_reg32_mem32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::LTR_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVSB(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVSD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVSW(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVSX_reg16_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVSX_reg32_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVSX_reg32_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVZX_reg16_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVZX_reg32_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVZX_reg32_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_AL_moff8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_AX_moff16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_CR_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_DR_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_EAX_moff32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_RM16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_RM16_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_RM16_seg(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_RM32_imm32(const X86::Instruction&) { TODO(); }
|
||||
|
||||
void SoftCPU::MOV_RM32_reg32(const X86::Instruction& insn)
|
||||
{
|
||||
ASSERT(insn.modrm().is_register());
|
||||
*m_reg32_table[insn.modrm().register_index()] = *m_reg32_table[insn.register_index()];
|
||||
}
|
||||
|
||||
void SoftCPU::MOV_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_RM8_reg8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_moff16_AX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_moff32_EAX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_moff8_AL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_reg16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_reg32_CR(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_reg32_DR(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
|
||||
void SoftCPU::MOV_reg32_imm32(const X86::Instruction& insn)
|
||||
{
|
||||
*m_reg32_table[insn.register_index()] = insn.imm32();
|
||||
}
|
||||
|
||||
void SoftCPU::MOV_reg8_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_reg8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_seg_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOV_seg_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MUL_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MUL_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MUL_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::NEG_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::NEG_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::NEG_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::NOP(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::NOT_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::NOT_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::NOT_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_AL_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_AX_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_EAX_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_RM16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_RM16_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_RM32_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_RM32_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_RM8_reg8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OR_reg8_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUTSB(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUTSD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUTSW(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUT_DX_AL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUT_DX_AX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUT_DX_EAX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUT_imm8_AL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUT_imm8_AX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::OUT_imm8_EAX(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PADDB_mm1_mm2m64(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PADDW_mm1_mm2m64(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PADDD_mm1_mm2m64(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POPA(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POPAD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POPF(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POPFD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_DS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_ES(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_FS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_GS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_SS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::POP_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSHA(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSHAD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSHF(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSHFD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_CS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_DS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_ES(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_FS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_GS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_SP_8086_80186(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_SS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::PUSH_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM16_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM32_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM8_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM8_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCL_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM16_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM32_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM8_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM8_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RCR_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RDTSC(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RET(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RETF(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RETF_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::RET_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM16_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM32_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM8_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM8_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROL_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM16_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM32_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM8_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM8_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::ROR_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAHF(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SALC(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM16_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM32_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM8_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM8_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SAR_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_AL_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_AX_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_EAX_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_RM16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_RM16_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_RM32_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_RM32_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_RM8_reg8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SBB_reg8_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SCASB(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SCASD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SCASW(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SETcc_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SGDT(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHLD_RM16_reg16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHLD_RM16_reg16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHLD_RM32_reg32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHLD_RM32_reg32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM16_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM32_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM8_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM8_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHL_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHRD_RM16_reg16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHRD_RM16_reg16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHRD_RM32_reg32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHRD_RM32_reg32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM16_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM16_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM32_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM32_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM8_1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM8_CL(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SHR_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SIDT(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SLDT_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SMSW_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::STC(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::STD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::STI(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::STOSB(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::STOSD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::STOSW(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::STR_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_AL_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_AX_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_EAX_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_RM16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_RM16_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_RM32_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_RM32_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_RM8_reg8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::SUB_reg8_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_AL_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_AX_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_EAX_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_RM16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_RM16_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_RM32_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_RM32_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::TEST_RM8_reg8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::UD0(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::UD1(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::UD2(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::VERR_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::VERW_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::WAIT(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::WBINVD(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XADD_RM16_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XADD_RM32_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XADD_RM8_reg8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XCHG_AX_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XCHG_EAX_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XCHG_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XCHG_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XCHG_reg8_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XLAT(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_AL_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_AX_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_EAX_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_RM16_imm16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_RM16_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_RM16_reg16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_RM32_imm32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_RM32_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_RM32_reg32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_RM8_imm8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_RM8_reg8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_reg16_RM16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_reg32_RM32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::XOR_reg8_RM8(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVQ_mm1_mm2m64(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::EMMS(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::MOVQ_mm1_m64_mm2(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xC0(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xC1_16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xC1_32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xD0(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xD1_16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xD1_32(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xD2(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xD3_16(const X86::Instruction&) { TODO(); }
|
||||
void SoftCPU::wrap_0xD3_32(const X86::Instruction&) { TODO(); }
|
||||
|
||||
}
|
||||
525
DevTools/UserspaceEmulator/SoftCPU.h
Normal file
525
DevTools/UserspaceEmulator/SoftCPU.h
Normal file
|
|
@ -0,0 +1,525 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <LibX86/Interpreter.h>
|
||||
|
||||
namespace UserspaceEmulator {
|
||||
|
||||
class Emulator;
|
||||
|
||||
class SoftCPU final : public X86::Interpreter {
|
||||
public:
|
||||
explicit SoftCPU(Emulator&);
|
||||
void dump() const;
|
||||
|
||||
virtual void AAA(const X86::Instruction&) override;
|
||||
virtual void AAD(const X86::Instruction&) override;
|
||||
virtual void AAM(const X86::Instruction&) override;
|
||||
virtual void AAS(const X86::Instruction&) override;
|
||||
virtual void ADC_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void ADC_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void ADC_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void ADC_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void ADC_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void ADC_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void ADC_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void ADC_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void ADC_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void ADC_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void ADC_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void ADC_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void ADC_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void ADC_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void ADD_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void ADD_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void ADD_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void ADD_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void ADD_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void ADD_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void ADD_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void ADD_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void ADD_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void ADD_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void ADD_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void ADD_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void ADD_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void ADD_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void AND_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void AND_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void AND_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void AND_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void AND_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void AND_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void AND_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void AND_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void AND_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void AND_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void AND_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void AND_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void AND_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void AND_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void ARPL(const X86::Instruction&) override;
|
||||
virtual void BOUND(const X86::Instruction&) override;
|
||||
virtual void BSF_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void BSF_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void BSR_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void BSR_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void BSWAP_reg32(const X86::Instruction&) override;
|
||||
virtual void BTC_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void BTC_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void BTC_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void BTC_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void BTR_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void BTR_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void BTR_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void BTR_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void BTS_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void BTS_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void BTS_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void BTS_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void BT_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void BT_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void BT_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void BT_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void CALL_FAR_mem16(const X86::Instruction&) override;
|
||||
virtual void CALL_FAR_mem32(const X86::Instruction&) override;
|
||||
virtual void CALL_RM16(const X86::Instruction&) override;
|
||||
virtual void CALL_RM32(const X86::Instruction&) override;
|
||||
virtual void CALL_imm16(const X86::Instruction&) override;
|
||||
virtual void CALL_imm16_imm16(const X86::Instruction&) override;
|
||||
virtual void CALL_imm16_imm32(const X86::Instruction&) override;
|
||||
virtual void CALL_imm32(const X86::Instruction&) override;
|
||||
virtual void CBW(const X86::Instruction&) override;
|
||||
virtual void CDQ(const X86::Instruction&) override;
|
||||
virtual void CLC(const X86::Instruction&) override;
|
||||
virtual void CLD(const X86::Instruction&) override;
|
||||
virtual void CLI(const X86::Instruction&) override;
|
||||
virtual void CLTS(const X86::Instruction&) override;
|
||||
virtual void CMC(const X86::Instruction&) override;
|
||||
virtual void CMOVcc_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void CMOVcc_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void CMPSB(const X86::Instruction&) override;
|
||||
virtual void CMPSD(const X86::Instruction&) override;
|
||||
virtual void CMPSW(const X86::Instruction&) override;
|
||||
virtual void CMPXCHG_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void CMPXCHG_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void CMPXCHG_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void CMP_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void CMP_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void CMP_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void CMP_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void CMP_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void CMP_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void CMP_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void CMP_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void CMP_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void CMP_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void CMP_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void CMP_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void CMP_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void CMP_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void CPUID(const X86::Instruction&) override;
|
||||
virtual void CWD(const X86::Instruction&) override;
|
||||
virtual void CWDE(const X86::Instruction&) override;
|
||||
virtual void DAA(const X86::Instruction&) override;
|
||||
virtual void DAS(const X86::Instruction&) override;
|
||||
virtual void DEC_RM16(const X86::Instruction&) override;
|
||||
virtual void DEC_RM32(const X86::Instruction&) override;
|
||||
virtual void DEC_RM8(const X86::Instruction&) override;
|
||||
virtual void DEC_reg16(const X86::Instruction&) override;
|
||||
virtual void DEC_reg32(const X86::Instruction&) override;
|
||||
virtual void DIV_RM16(const X86::Instruction&) override;
|
||||
virtual void DIV_RM32(const X86::Instruction&) override;
|
||||
virtual void DIV_RM8(const X86::Instruction&) override;
|
||||
virtual void ENTER16(const X86::Instruction&) override;
|
||||
virtual void ENTER32(const X86::Instruction&) override;
|
||||
virtual void ESCAPE(const X86::Instruction&) override;
|
||||
virtual void HLT(const X86::Instruction&) override;
|
||||
virtual void IDIV_RM16(const X86::Instruction&) override;
|
||||
virtual void IDIV_RM32(const X86::Instruction&) override;
|
||||
virtual void IDIV_RM8(const X86::Instruction&) override;
|
||||
virtual void IMUL_RM16(const X86::Instruction&) override;
|
||||
virtual void IMUL_RM32(const X86::Instruction&) override;
|
||||
virtual void IMUL_RM8(const X86::Instruction&) override;
|
||||
virtual void IMUL_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void IMUL_reg16_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void IMUL_reg16_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void IMUL_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void IMUL_reg32_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void IMUL_reg32_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void INC_RM16(const X86::Instruction&) override;
|
||||
virtual void INC_RM32(const X86::Instruction&) override;
|
||||
virtual void INC_RM8(const X86::Instruction&) override;
|
||||
virtual void INC_reg16(const X86::Instruction&) override;
|
||||
virtual void INC_reg32(const X86::Instruction&) override;
|
||||
virtual void INSB(const X86::Instruction&) override;
|
||||
virtual void INSD(const X86::Instruction&) override;
|
||||
virtual void INSW(const X86::Instruction&) override;
|
||||
virtual void INT3(const X86::Instruction&) override;
|
||||
virtual void INTO(const X86::Instruction&) override;
|
||||
virtual void INT_imm8(const X86::Instruction&) override;
|
||||
virtual void INVLPG(const X86::Instruction&) override;
|
||||
virtual void IN_AL_DX(const X86::Instruction&) override;
|
||||
virtual void IN_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void IN_AX_DX(const X86::Instruction&) override;
|
||||
virtual void IN_AX_imm8(const X86::Instruction&) override;
|
||||
virtual void IN_EAX_DX(const X86::Instruction&) override;
|
||||
virtual void IN_EAX_imm8(const X86::Instruction&) override;
|
||||
virtual void IRET(const X86::Instruction&) override;
|
||||
virtual void JCXZ_imm8(const X86::Instruction&) override;
|
||||
virtual void JMP_FAR_mem16(const X86::Instruction&) override;
|
||||
virtual void JMP_FAR_mem32(const X86::Instruction&) override;
|
||||
virtual void JMP_RM16(const X86::Instruction&) override;
|
||||
virtual void JMP_RM32(const X86::Instruction&) override;
|
||||
virtual void JMP_imm16(const X86::Instruction&) override;
|
||||
virtual void JMP_imm16_imm16(const X86::Instruction&) override;
|
||||
virtual void JMP_imm16_imm32(const X86::Instruction&) override;
|
||||
virtual void JMP_imm32(const X86::Instruction&) override;
|
||||
virtual void JMP_short_imm8(const X86::Instruction&) override;
|
||||
virtual void Jcc_NEAR_imm(const X86::Instruction&) override;
|
||||
virtual void Jcc_imm8(const X86::Instruction&) override;
|
||||
virtual void LAHF(const X86::Instruction&) override;
|
||||
virtual void LAR_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void LAR_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void LDS_reg16_mem16(const X86::Instruction&) override;
|
||||
virtual void LDS_reg32_mem32(const X86::Instruction&) override;
|
||||
virtual void LEAVE16(const X86::Instruction&) override;
|
||||
virtual void LEAVE32(const X86::Instruction&) override;
|
||||
virtual void LEA_reg16_mem16(const X86::Instruction&) override;
|
||||
virtual void LEA_reg32_mem32(const X86::Instruction&) override;
|
||||
virtual void LES_reg16_mem16(const X86::Instruction&) override;
|
||||
virtual void LES_reg32_mem32(const X86::Instruction&) override;
|
||||
virtual void LFS_reg16_mem16(const X86::Instruction&) override;
|
||||
virtual void LFS_reg32_mem32(const X86::Instruction&) override;
|
||||
virtual void LGDT(const X86::Instruction&) override;
|
||||
virtual void LGS_reg16_mem16(const X86::Instruction&) override;
|
||||
virtual void LGS_reg32_mem32(const X86::Instruction&) override;
|
||||
virtual void LIDT(const X86::Instruction&) override;
|
||||
virtual void LLDT_RM16(const X86::Instruction&) override;
|
||||
virtual void LMSW_RM16(const X86::Instruction&) override;
|
||||
virtual void LODSB(const X86::Instruction&) override;
|
||||
virtual void LODSD(const X86::Instruction&) override;
|
||||
virtual void LODSW(const X86::Instruction&) override;
|
||||
virtual void LOOPNZ_imm8(const X86::Instruction&) override;
|
||||
virtual void LOOPZ_imm8(const X86::Instruction&) override;
|
||||
virtual void LOOP_imm8(const X86::Instruction&) override;
|
||||
virtual void LSL_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void LSL_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void LSS_reg16_mem16(const X86::Instruction&) override;
|
||||
virtual void LSS_reg32_mem32(const X86::Instruction&) override;
|
||||
virtual void LTR_RM16(const X86::Instruction&) override;
|
||||
virtual void MOVSB(const X86::Instruction&) override;
|
||||
virtual void MOVSD(const X86::Instruction&) override;
|
||||
virtual void MOVSW(const X86::Instruction&) override;
|
||||
virtual void MOVSX_reg16_RM8(const X86::Instruction&) override;
|
||||
virtual void MOVSX_reg32_RM16(const X86::Instruction&) override;
|
||||
virtual void MOVSX_reg32_RM8(const X86::Instruction&) override;
|
||||
virtual void MOVZX_reg16_RM8(const X86::Instruction&) override;
|
||||
virtual void MOVZX_reg32_RM16(const X86::Instruction&) override;
|
||||
virtual void MOVZX_reg32_RM8(const X86::Instruction&) override;
|
||||
virtual void MOV_AL_moff8(const X86::Instruction&) override;
|
||||
virtual void MOV_AX_moff16(const X86::Instruction&) override;
|
||||
virtual void MOV_CR_reg32(const X86::Instruction&) override;
|
||||
virtual void MOV_DR_reg32(const X86::Instruction&) override;
|
||||
virtual void MOV_EAX_moff32(const X86::Instruction&) override;
|
||||
virtual void MOV_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void MOV_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void MOV_RM16_seg(const X86::Instruction&) override;
|
||||
virtual void MOV_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void MOV_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void MOV_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void MOV_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void MOV_moff16_AX(const X86::Instruction&) override;
|
||||
virtual void MOV_moff32_EAX(const X86::Instruction&) override;
|
||||
virtual void MOV_moff8_AL(const X86::Instruction&) override;
|
||||
virtual void MOV_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void MOV_reg16_imm16(const X86::Instruction&) override;
|
||||
virtual void MOV_reg32_CR(const X86::Instruction&) override;
|
||||
virtual void MOV_reg32_DR(const X86::Instruction&) override;
|
||||
virtual void MOV_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void MOV_reg32_imm32(const X86::Instruction&) override;
|
||||
virtual void MOV_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void MOV_reg8_imm8(const X86::Instruction&) override;
|
||||
virtual void MOV_seg_RM16(const X86::Instruction&) override;
|
||||
virtual void MOV_seg_RM32(const X86::Instruction&) override;
|
||||
virtual void MUL_RM16(const X86::Instruction&) override;
|
||||
virtual void MUL_RM32(const X86::Instruction&) override;
|
||||
virtual void MUL_RM8(const X86::Instruction&) override;
|
||||
virtual void NEG_RM16(const X86::Instruction&) override;
|
||||
virtual void NEG_RM32(const X86::Instruction&) override;
|
||||
virtual void NEG_RM8(const X86::Instruction&) override;
|
||||
virtual void NOP(const X86::Instruction&) override;
|
||||
virtual void NOT_RM16(const X86::Instruction&) override;
|
||||
virtual void NOT_RM32(const X86::Instruction&) override;
|
||||
virtual void NOT_RM8(const X86::Instruction&) override;
|
||||
virtual void OR_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void OR_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void OR_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void OR_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void OR_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void OR_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void OR_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void OR_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void OR_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void OR_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void OR_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void OR_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void OR_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void OR_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void OUTSB(const X86::Instruction&) override;
|
||||
virtual void OUTSD(const X86::Instruction&) override;
|
||||
virtual void OUTSW(const X86::Instruction&) override;
|
||||
virtual void OUT_DX_AL(const X86::Instruction&) override;
|
||||
virtual void OUT_DX_AX(const X86::Instruction&) override;
|
||||
virtual void OUT_DX_EAX(const X86::Instruction&) override;
|
||||
virtual void OUT_imm8_AL(const X86::Instruction&) override;
|
||||
virtual void OUT_imm8_AX(const X86::Instruction&) override;
|
||||
virtual void OUT_imm8_EAX(const X86::Instruction&) override;
|
||||
virtual void PADDB_mm1_mm2m64(const X86::Instruction&) override;
|
||||
virtual void PADDW_mm1_mm2m64(const X86::Instruction&) override;
|
||||
virtual void PADDD_mm1_mm2m64(const X86::Instruction&) override;
|
||||
virtual void POPA(const X86::Instruction&) override;
|
||||
virtual void POPAD(const X86::Instruction&) override;
|
||||
virtual void POPF(const X86::Instruction&) override;
|
||||
virtual void POPFD(const X86::Instruction&) override;
|
||||
virtual void POP_DS(const X86::Instruction&) override;
|
||||
virtual void POP_ES(const X86::Instruction&) override;
|
||||
virtual void POP_FS(const X86::Instruction&) override;
|
||||
virtual void POP_GS(const X86::Instruction&) override;
|
||||
virtual void POP_RM16(const X86::Instruction&) override;
|
||||
virtual void POP_RM32(const X86::Instruction&) override;
|
||||
virtual void POP_SS(const X86::Instruction&) override;
|
||||
virtual void POP_reg16(const X86::Instruction&) override;
|
||||
virtual void POP_reg32(const X86::Instruction&) override;
|
||||
virtual void PUSHA(const X86::Instruction&) override;
|
||||
virtual void PUSHAD(const X86::Instruction&) override;
|
||||
virtual void PUSHF(const X86::Instruction&) override;
|
||||
virtual void PUSHFD(const X86::Instruction&) override;
|
||||
virtual void PUSH_CS(const X86::Instruction&) override;
|
||||
virtual void PUSH_DS(const X86::Instruction&) override;
|
||||
virtual void PUSH_ES(const X86::Instruction&) override;
|
||||
virtual void PUSH_FS(const X86::Instruction&) override;
|
||||
virtual void PUSH_GS(const X86::Instruction&) override;
|
||||
virtual void PUSH_RM16(const X86::Instruction&) override;
|
||||
virtual void PUSH_RM32(const X86::Instruction&) override;
|
||||
virtual void PUSH_SP_8086_80186(const X86::Instruction&) override;
|
||||
virtual void PUSH_SS(const X86::Instruction&) override;
|
||||
virtual void PUSH_imm16(const X86::Instruction&) override;
|
||||
virtual void PUSH_imm32(const X86::Instruction&) override;
|
||||
virtual void PUSH_imm8(const X86::Instruction&) override;
|
||||
virtual void PUSH_reg16(const X86::Instruction&) override;
|
||||
virtual void PUSH_reg32(const X86::Instruction&) override;
|
||||
virtual void RCL_RM16_1(const X86::Instruction&) override;
|
||||
virtual void RCL_RM16_CL(const X86::Instruction&) override;
|
||||
virtual void RCL_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void RCL_RM32_1(const X86::Instruction&) override;
|
||||
virtual void RCL_RM32_CL(const X86::Instruction&) override;
|
||||
virtual void RCL_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void RCL_RM8_1(const X86::Instruction&) override;
|
||||
virtual void RCL_RM8_CL(const X86::Instruction&) override;
|
||||
virtual void RCL_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void RCR_RM16_1(const X86::Instruction&) override;
|
||||
virtual void RCR_RM16_CL(const X86::Instruction&) override;
|
||||
virtual void RCR_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void RCR_RM32_1(const X86::Instruction&) override;
|
||||
virtual void RCR_RM32_CL(const X86::Instruction&) override;
|
||||
virtual void RCR_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void RCR_RM8_1(const X86::Instruction&) override;
|
||||
virtual void RCR_RM8_CL(const X86::Instruction&) override;
|
||||
virtual void RCR_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void RDTSC(const X86::Instruction&) override;
|
||||
virtual void RET(const X86::Instruction&) override;
|
||||
virtual void RETF(const X86::Instruction&) override;
|
||||
virtual void RETF_imm16(const X86::Instruction&) override;
|
||||
virtual void RET_imm16(const X86::Instruction&) override;
|
||||
virtual void ROL_RM16_1(const X86::Instruction&) override;
|
||||
virtual void ROL_RM16_CL(const X86::Instruction&) override;
|
||||
virtual void ROL_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void ROL_RM32_1(const X86::Instruction&) override;
|
||||
virtual void ROL_RM32_CL(const X86::Instruction&) override;
|
||||
virtual void ROL_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void ROL_RM8_1(const X86::Instruction&) override;
|
||||
virtual void ROL_RM8_CL(const X86::Instruction&) override;
|
||||
virtual void ROL_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void ROR_RM16_1(const X86::Instruction&) override;
|
||||
virtual void ROR_RM16_CL(const X86::Instruction&) override;
|
||||
virtual void ROR_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void ROR_RM32_1(const X86::Instruction&) override;
|
||||
virtual void ROR_RM32_CL(const X86::Instruction&) override;
|
||||
virtual void ROR_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void ROR_RM8_1(const X86::Instruction&) override;
|
||||
virtual void ROR_RM8_CL(const X86::Instruction&) override;
|
||||
virtual void ROR_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void SAHF(const X86::Instruction&) override;
|
||||
virtual void SALC(const X86::Instruction&) override;
|
||||
virtual void SAR_RM16_1(const X86::Instruction&) override;
|
||||
virtual void SAR_RM16_CL(const X86::Instruction&) override;
|
||||
virtual void SAR_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void SAR_RM32_1(const X86::Instruction&) override;
|
||||
virtual void SAR_RM32_CL(const X86::Instruction&) override;
|
||||
virtual void SAR_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void SAR_RM8_1(const X86::Instruction&) override;
|
||||
virtual void SAR_RM8_CL(const X86::Instruction&) override;
|
||||
virtual void SAR_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void SBB_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void SBB_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void SBB_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void SBB_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void SBB_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void SBB_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void SBB_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void SBB_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void SBB_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void SBB_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void SBB_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void SBB_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void SBB_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void SBB_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void SCASB(const X86::Instruction&) override;
|
||||
virtual void SCASD(const X86::Instruction&) override;
|
||||
virtual void SCASW(const X86::Instruction&) override;
|
||||
virtual void SETcc_RM8(const X86::Instruction&) override;
|
||||
virtual void SGDT(const X86::Instruction&) override;
|
||||
virtual void SHLD_RM16_reg16_CL(const X86::Instruction&) override;
|
||||
virtual void SHLD_RM16_reg16_imm8(const X86::Instruction&) override;
|
||||
virtual void SHLD_RM32_reg32_CL(const X86::Instruction&) override;
|
||||
virtual void SHLD_RM32_reg32_imm8(const X86::Instruction&) override;
|
||||
virtual void SHL_RM16_1(const X86::Instruction&) override;
|
||||
virtual void SHL_RM16_CL(const X86::Instruction&) override;
|
||||
virtual void SHL_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void SHL_RM32_1(const X86::Instruction&) override;
|
||||
virtual void SHL_RM32_CL(const X86::Instruction&) override;
|
||||
virtual void SHL_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void SHL_RM8_1(const X86::Instruction&) override;
|
||||
virtual void SHL_RM8_CL(const X86::Instruction&) override;
|
||||
virtual void SHL_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void SHRD_RM16_reg16_CL(const X86::Instruction&) override;
|
||||
virtual void SHRD_RM16_reg16_imm8(const X86::Instruction&) override;
|
||||
virtual void SHRD_RM32_reg32_CL(const X86::Instruction&) override;
|
||||
virtual void SHRD_RM32_reg32_imm8(const X86::Instruction&) override;
|
||||
virtual void SHR_RM16_1(const X86::Instruction&) override;
|
||||
virtual void SHR_RM16_CL(const X86::Instruction&) override;
|
||||
virtual void SHR_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void SHR_RM32_1(const X86::Instruction&) override;
|
||||
virtual void SHR_RM32_CL(const X86::Instruction&) override;
|
||||
virtual void SHR_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void SHR_RM8_1(const X86::Instruction&) override;
|
||||
virtual void SHR_RM8_CL(const X86::Instruction&) override;
|
||||
virtual void SHR_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void SIDT(const X86::Instruction&) override;
|
||||
virtual void SLDT_RM16(const X86::Instruction&) override;
|
||||
virtual void SMSW_RM16(const X86::Instruction&) override;
|
||||
virtual void STC(const X86::Instruction&) override;
|
||||
virtual void STD(const X86::Instruction&) override;
|
||||
virtual void STI(const X86::Instruction&) override;
|
||||
virtual void STOSB(const X86::Instruction&) override;
|
||||
virtual void STOSD(const X86::Instruction&) override;
|
||||
virtual void STOSW(const X86::Instruction&) override;
|
||||
virtual void STR_RM16(const X86::Instruction&) override;
|
||||
virtual void SUB_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void SUB_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void SUB_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void SUB_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void SUB_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void SUB_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void SUB_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void SUB_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void SUB_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void SUB_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void SUB_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void SUB_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void SUB_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void SUB_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void TEST_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void TEST_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void TEST_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void TEST_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void TEST_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void TEST_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void TEST_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void TEST_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void TEST_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void UD0(const X86::Instruction&) override;
|
||||
virtual void UD1(const X86::Instruction&) override;
|
||||
virtual void UD2(const X86::Instruction&) override;
|
||||
virtual void VERR_RM16(const X86::Instruction&) override;
|
||||
virtual void VERW_RM16(const X86::Instruction&) override;
|
||||
virtual void WAIT(const X86::Instruction&) override;
|
||||
virtual void WBINVD(const X86::Instruction&) override;
|
||||
virtual void XADD_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void XADD_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void XADD_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void XCHG_AX_reg16(const X86::Instruction&) override;
|
||||
virtual void XCHG_EAX_reg32(const X86::Instruction&) override;
|
||||
virtual void XCHG_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void XCHG_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void XCHG_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void XLAT(const X86::Instruction&) override;
|
||||
virtual void XOR_AL_imm8(const X86::Instruction&) override;
|
||||
virtual void XOR_AX_imm16(const X86::Instruction&) override;
|
||||
virtual void XOR_EAX_imm32(const X86::Instruction&) override;
|
||||
virtual void XOR_RM16_imm16(const X86::Instruction&) override;
|
||||
virtual void XOR_RM16_imm8(const X86::Instruction&) override;
|
||||
virtual void XOR_RM16_reg16(const X86::Instruction&) override;
|
||||
virtual void XOR_RM32_imm32(const X86::Instruction&) override;
|
||||
virtual void XOR_RM32_imm8(const X86::Instruction&) override;
|
||||
virtual void XOR_RM32_reg32(const X86::Instruction&) override;
|
||||
virtual void XOR_RM8_imm8(const X86::Instruction&) override;
|
||||
virtual void XOR_RM8_reg8(const X86::Instruction&) override;
|
||||
virtual void XOR_reg16_RM16(const X86::Instruction&) override;
|
||||
virtual void XOR_reg32_RM32(const X86::Instruction&) override;
|
||||
virtual void XOR_reg8_RM8(const X86::Instruction&) override;
|
||||
virtual void MOVQ_mm1_mm2m64(const X86::Instruction&) override;
|
||||
virtual void EMMS(const X86::Instruction&) override;
|
||||
virtual void MOVQ_mm1_m64_mm2(const X86::Instruction&) override;
|
||||
virtual void wrap_0xC0(const X86::Instruction&) override;
|
||||
virtual void wrap_0xC1_16(const X86::Instruction&) override;
|
||||
virtual void wrap_0xC1_32(const X86::Instruction&) override;
|
||||
virtual void wrap_0xD0(const X86::Instruction&) override;
|
||||
virtual void wrap_0xD1_16(const X86::Instruction&) override;
|
||||
virtual void wrap_0xD1_32(const X86::Instruction&) override;
|
||||
virtual void wrap_0xD2(const X86::Instruction&) override;
|
||||
virtual void wrap_0xD3_16(const X86::Instruction&) override;
|
||||
virtual void wrap_0xD3_32(const X86::Instruction&) override;
|
||||
|
||||
private:
|
||||
Emulator& m_emulator;
|
||||
|
||||
u32* m_reg32_table[8];
|
||||
|
||||
u32 m_eax { 0 };
|
||||
u32 m_ebx { 0 };
|
||||
u32 m_ecx { 0 };
|
||||
u32 m_edx { 0 };
|
||||
u32 m_esp { 0 };
|
||||
u32 m_ebp { 0 };
|
||||
u32 m_esi { 0 };
|
||||
u32 m_edi { 0 };
|
||||
};
|
||||
|
||||
}
|
||||
62
DevTools/UserspaceEmulator/main.cpp
Normal file
62
DevTools/UserspaceEmulator/main.cpp
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "Emulator.h"
|
||||
#include "SoftCPU.h"
|
||||
#include <AK/LogStream.h>
|
||||
#include <AK/MappedFile.h>
|
||||
#include <LibCore/ArgsParser.h>
|
||||
#include <LibELF/Loader.h>
|
||||
#include <LibX86/Instruction.h>
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
const char* executable_path = nullptr;
|
||||
|
||||
Core::ArgsParser args_parser;
|
||||
args_parser.add_positional_argument(executable_path, "Executable path", "executable");
|
||||
args_parser.parse(argc, argv);
|
||||
|
||||
MappedFile mapped_file(executable_path);
|
||||
if (!mapped_file.is_valid()) {
|
||||
warn() << "Unable to map " << executable_path;
|
||||
return 1;
|
||||
}
|
||||
|
||||
auto elf = ELF::Loader::create((const u8*)mapped_file.data(), mapped_file.size());
|
||||
|
||||
auto main_symbol = elf->find_demangled_function("main");
|
||||
if (!main_symbol.has_value()) {
|
||||
warn() << "Could not find 'main' symbol in executable";
|
||||
return 1;
|
||||
}
|
||||
|
||||
auto main_code = main_symbol.value().raw_data();
|
||||
X86::SimpleInstructionStream stream((const u8*)main_code.characters_without_null_termination(), main_code.length());
|
||||
|
||||
UserspaceEmulator::Emulator emulator;
|
||||
return emulator.exec(stream, main_symbol.value().value());
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue