Kernel/PCI: Introduce a new ECAM access mechanism

Now the kernel supports 2 ECAM access methods.
MMIOAccess was renamed to WindowedMMIOAccess and is what we had until
now - each device that is detected on boot is assigned to a
memory-mapped window, so IO operations on multiple devices can occur
simultaneously due to creating multiple virtual mappings, hence the name
is a memory-mapped window.

This commit adds a new class called MMIOAccess (not to be confused with
the old MMIOAccess class). This class creates one memory-mapped window.
On each IO operation on a configuration space of a device, it maps the
requested PCI bus region to that window. Therefore it holds a SpinLock
during the operation to ensure that no other PCI bus region was mapped
during the call.

A user can choose to either use PCI ECAM with memory-mapped window
for each device, or for an entire bus. By default, the kernel prefers to
map the entire PCI bus region.

Kernel/CMakeLists.txt

@@ -115,8 +115,9 @@ set(KERNEL_SOURCES
     PCI/Device.cpp
     PCI/DeviceController.cpp
     PCI/IOAccess.cpp
-    PCI/Initializer.cpp
     PCI/MMIOAccess.cpp
+    PCI/Initializer.cpp
+    PCI/WindowedMMIOAccess.cpp
     Panic.cpp
     PerformanceEventBuffer.cpp
     Process.cpp

Kernel/CommandLine.cpp

@@ -108,13 +108,15 @@ UNMAP_AFTER_INIT bool CommandLine::is_vmmouse_enabled() const
     return lookup("vmmouse").value_or("on") == "on";
 }
 
-UNMAP_AFTER_INIT bool CommandLine::is_pci_ecam_enabled() const
+UNMAP_AFTER_INIT PCIAccessLevel CommandLine::pci_access_level() const
 {
     auto value = lookup("pci_ecam").value_or("on");
     if (value == "on")
-        return true;
+        return PCIAccessLevel::MappingPerBus;
+    if (value == "per-device")
+        return PCIAccessLevel::MappingPerDevice;
     if (value == "off")
-        return false;
+        return PCIAccessLevel::IOAddressing;
     PANIC("Unknown PCI ECAM setting: {}", value);
 }
 

Kernel/CommandLine.h

@@ -50,6 +50,12 @@ enum class AcpiFeatureLevel {
     Disabled,
 };
 
+enum class PCIAccessLevel {
+    IOAddressing,
+    MappingPerBus,
+    MappingPerDevice,
+};
+
 enum class AHCIResetMode {
     ControllerOnly,
     Complete,
@@ -71,7 +77,7 @@ public:
     [[nodiscard]] bool is_ide_enabled() const;
     [[nodiscard]] bool is_smp_enabled() const;
     [[nodiscard]] bool is_vmmouse_enabled() const;
-    [[nodiscard]] bool is_pci_ecam_enabled() const;
+    [[nodiscard]] PCIAccessLevel pci_access_level() const;
     [[nodiscard]] bool is_legacy_time_enabled() const;
     [[nodiscard]] bool is_text_mode() const;
     [[nodiscard]] bool is_force_pio() const;

Kernel/PCI/Access.h

@@ -34,11 +34,6 @@ namespace Kernel {
 
 class PCI::Access {
 public:
-    enum class Type {
-        IO,
-        MMIO,
-    };
-
     void enumerate(Function<void(Address, ID)>&) const;
 
     void enumerate_bus(int type, u8 bus, Function<void(Address, ID)>&, bool recursive);

Kernel/PCI/Definitions.h

@@ -226,6 +226,7 @@ PhysicalID get_physical_id(Address address);
 
 class Access;
 class MMIOAccess;
+class WindowedMMIOAccess;
 class IOAccess;
 class MMIOSegment;
 class DeviceController;

Kernel/PCI/IOAccess.h

@@ -40,7 +40,7 @@ protected:
 
 private:
     virtual void enumerate_hardware(Function<void(Address, ID)>) override;
-    virtual const char* access_type() const override { return "IO-Access"; };
+    virtual const char* access_type() const override { return "IOAccess"; };
     virtual uint32_t segment_count() const override { return 1; };
     virtual void write8_field(Address address, u32, u8) override final;
     virtual void write16_field(Address address, u32, u16) override final;

Kernel/PCI/Initializer.cpp

@@ -30,6 +30,7 @@
 #include <Kernel/PCI/IOAccess.h>
 #include <Kernel/PCI/Initializer.h>
 #include <Kernel/PCI/MMIOAccess.h>
+#include <Kernel/PCI/WindowedMMIOAccess.h>
 #include <Kernel/Panic.h>
 
 namespace Kernel {
@@ -37,25 +38,38 @@ namespace PCI {
 
 static bool test_pci_io();
 
-UNMAP_AFTER_INIT static Access::Type detect_optimal_access_type(bool mmio_allowed)
+UNMAP_AFTER_INIT static PCIAccessLevel detect_optimal_access_type(PCIAccessLevel boot_determined)
 {
-    if (mmio_allowed && ACPI::is_enabled() && !ACPI::Parser::the()->find_table("MCFG").is_null())
-        return Access::Type::MMIO;
+    if (!ACPI::is_enabled() || ACPI::Parser::the()->find_table("MCFG").is_null())
+        return PCIAccessLevel::IOAddressing;
+
+    if (boot_determined != PCIAccessLevel::IOAddressing)
+        return boot_determined;
 
     if (test_pci_io())
-        return Access::Type::IO;
+        return PCIAccessLevel::IOAddressing;
 
     PANIC("No PCI bus access method detected!");
 }
 
 UNMAP_AFTER_INIT void initialize()
 {
-    bool mmio_allowed = kernel_command_line().is_pci_ecam_enabled();
+    auto boot_determined = kernel_command_line().pci_access_level();
 
-    if (detect_optimal_access_type(mmio_allowed) == Access::Type::MMIO)
+    switch (detect_optimal_access_type(boot_determined)) {
+    case PCIAccessLevel::MappingPerDevice:
+        WindowedMMIOAccess::initialize(ACPI::Parser::the()->find_table("MCFG"));
+        break;
+    case PCIAccessLevel::MappingPerBus:
         MMIOAccess::initialize(ACPI::Parser::the()->find_table("MCFG"));
-    else
+        break;
+    case PCIAccessLevel::IOAddressing:
         IOAccess::initialize();
+        break;
+    default:
+        VERIFY_NOT_REACHED();
+    }
+
     PCI::enumerate([&](const Address& address, ID id) {
         dmesgln("{} {}", address, id);
     });

Kernel/PCI/MMIOAccess.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
+ * Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -33,52 +33,35 @@
 namespace Kernel {
 namespace PCI {
 
-class MMIOSegment {
-public:
-    MMIOSegment(PhysicalAddress, u8, u8);
-    u8 get_start_bus() const;
-    u8 get_end_bus() const;
-    size_t get_size() const;
-    PhysicalAddress get_paddr() const;
+#define MEMORY_RANGE_PER_BUS (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS)
 
-private:
-    PhysicalAddress m_base_addr;
-    u8 m_start_bus;
-    u8 m_end_bus;
-};
-
-#define PCI_MMIO_CONFIG_SPACE_SIZE 4096
-
-UNMAP_AFTER_INIT DeviceConfigurationSpaceMapping::DeviceConfigurationSpaceMapping(Address device_address, const MMIOSegment& mmio_segment)
-    : m_device_address(device_address)
-    , m_mapped_region(MM.allocate_kernel_region(page_round_up(PCI_MMIO_CONFIG_SPACE_SIZE), "PCI MMIO Device Access", Region::Access::Read | Region::Access::Write).release_nonnull())
-{
-    PhysicalAddress segment_lower_addr = mmio_segment.get_paddr();
-    PhysicalAddress device_physical_mmio_space = segment_lower_addr.offset(
-        PCI_MMIO_CONFIG_SPACE_SIZE * m_device_address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * m_device_address.device() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS) * (m_device_address.bus() - mmio_segment.get_start_bus()));
-    m_mapped_region->physical_page_slot(0) = PhysicalPage::create(device_physical_mmio_space, false, false);
-    m_mapped_region->remap();
-}
-
-uint32_t MMIOAccess::segment_count() const
+u32 MMIOAccess::segment_count() const
 {
     return m_segments.size();
 }
 
-uint8_t MMIOAccess::segment_start_bus(u32 seg) const
+u8 MMIOAccess::segment_start_bus(u32 seg) const
 {
     auto segment = m_segments.get(seg);
     VERIFY(segment.has_value());
     return segment.value().get_start_bus();
 }
 
-uint8_t MMIOAccess::segment_end_bus(u32 seg) const
+u8 MMIOAccess::segment_end_bus(u32 seg) const
 {
     auto segment = m_segments.get(seg);
     VERIFY(segment.has_value());
     return segment.value().get_end_bus();
 }
 
+PhysicalAddress MMIOAccess::determine_memory_mapped_bus_region(u32 segment, u8 bus) const
+{
+    VERIFY(bus >= segment_start_bus(segment) && bus <= segment_end_bus(segment));
+    auto seg = m_segments.get(segment);
+    VERIFY(seg.has_value());
+    return seg.value().get_paddr().offset(MEMORY_RANGE_PER_BUS * (bus - seg.value().get_start_bus()));
+}
+
 UNMAP_AFTER_INIT void MMIOAccess::initialize(PhysicalAddress mcfg)
 {
     if (!Access::is_initialized()) {
@@ -118,77 +101,78 @@ UNMAP_AFTER_INIT MMIOAccess::MMIOAccess(PhysicalAddress p_mcfg)
     dmesgln("PCI: MMIO segments: {}", m_segments.size());
 
     InterruptDisabler disabler;
+    VERIFY(m_segments.contains(0));
+
+    // Note: we need to map this region before enumerating the hardware and adding
+    // PCI::PhysicalID objects to the vector, because get_capabilities calls
+    // PCI::read16 which will need this region to be mapped.
+    m_mapped_region = MM.allocate_kernel_region(determine_memory_mapped_bus_region(0, m_segments.get(0).value().get_start_bus()), MEMORY_RANGE_PER_BUS, "PCI ECAM", Region::Access::Read | Region::Access::Write);
+    dmesgln("PCI ECAM Mapped region @ {}", m_mapped_region->vaddr());
 
     enumerate_hardware([&](const Address& address, ID id) {
-        m_mapped_device_regions.append(make<DeviceConfigurationSpaceMapping>(address, m_segments.get(address.seg()).value()));
         m_physical_ids.append({ address, id, get_capabilities(address) });
-        dbgln_if(PCI_DEBUG, "PCI: Mapping device @ pci ({}) {} {}", address, m_mapped_device_regions.last().vaddr(), m_mapped_device_regions.last().paddr());
     });
 }
+void MMIOAccess::map_bus_region(u32 segment, u8 bus)
+{
+    VERIFY(m_access_lock.is_locked());
+    if (m_mapped_bus == bus)
+        return;
+    m_mapped_region = MM.allocate_kernel_region(determine_memory_mapped_bus_region(segment, bus), MEMORY_RANGE_PER_BUS, "PCI ECAM", Region::Access::Read | Region::Access::Write);
+}
 
-Optional<VirtualAddress> MMIOAccess::get_device_configuration_space(Address address)
+VirtualAddress MMIOAccess::get_device_configuration_space(Address address)
 {
+    VERIFY(m_access_lock.is_locked());
     dbgln_if(PCI_DEBUG, "PCI: Getting device configuration space for {}", address);
-    for (auto& mapping : m_mapped_device_regions) {
-        auto checked_address = mapping.address();
-        dbgln_if(PCI_DEBUG, "PCI Device Configuration Space Mapping: Check if {} was requested", checked_address);
-        if (address.seg() == checked_address.seg()
-            && address.bus() == checked_address.bus()
-            && address.device() == checked_address.device()
-            && address.function() == checked_address.function()) {
-            dbgln_if(PCI_DEBUG, "PCI Device Configuration Space Mapping: Found {}", checked_address);
-            return mapping.vaddr();
-        }
-    }
-
-    dbgln_if(PCI_DEBUG, "PCI: No device configuration space found for {}", address);
-    return {};
+    map_bus_region(address.seg(), address.bus());
+    return m_mapped_region->vaddr().offset(PCI_MMIO_CONFIG_SPACE_SIZE * address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * address.device());
 }
 
 u8 MMIOAccess::read8_field(Address address, u32 field)
 {
-    InterruptDisabler disabler;
+    ScopedSpinLock lock(m_access_lock);
     VERIFY(field <= 0xfff);
     dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 8-bit field {:#08x} for {}", field, address);
-    return *((u8*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
+    return *((volatile u8*)(get_device_configuration_space(address).get() + (field & 0xfff)));
 }
 
 u16 MMIOAccess::read16_field(Address address, u32 field)
 {
-    InterruptDisabler disabler;
+    ScopedSpinLock lock(m_access_lock);
     VERIFY(field < 0xfff);
     dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 16-bit field {:#08x} for {}", field, address);
-    return *((u16*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
+    return *((volatile u16*)(get_device_configuration_space(address).get() + (field & 0xfff)));
 }
 
 u32 MMIOAccess::read32_field(Address address, u32 field)
 {
-    InterruptDisabler disabler;
+    ScopedSpinLock lock(m_access_lock);
     VERIFY(field <= 0xffc);
     dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 32-bit field {:#08x} for {}", field, address);
-    return *((u32*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
+    return *((volatile u32*)(get_device_configuration_space(address).get() + (field & 0xfff)));
 }
 
 void MMIOAccess::write8_field(Address address, u32 field, u8 value)
 {
-    InterruptDisabler disabler;
+    ScopedSpinLock lock(m_access_lock);
     VERIFY(field <= 0xfff);
     dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 8-bit field {:#08x}, value={:#02x} for {}", field, value, address);
-    *((u8*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
+    *((volatile u8*)(get_device_configuration_space(address).get() + (field & 0xfff))) = value;
 }
 void MMIOAccess::write16_field(Address address, u32 field, u16 value)
 {
-    InterruptDisabler disabler;
+    ScopedSpinLock lock(m_access_lock);
     VERIFY(field < 0xfff);
     dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 16-bit field {:#08x}, value={:#02x} for {}", field, value, address);
-    *((u16*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
+    *((volatile u16*)(get_device_configuration_space(address).get() + (field & 0xfff))) = value;
 }
 void MMIOAccess::write32_field(Address address, u32 field, u32 value)
 {
-    InterruptDisabler disabler;
+    ScopedSpinLock lock(m_access_lock);
     VERIFY(field <= 0xffc);
     dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 32-bit field {:#08x}, value={:#02x} for {}", field, value, address);
-    *((u32*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
+    *((volatile u32*)(get_device_configuration_space(address).get() + (field & 0xfff))) = value;
 }
 
 void MMIOAccess::enumerate_hardware(Function<void(Address, ID)> callback)
@@ -210,29 +194,29 @@ void MMIOAccess::enumerate_hardware(Function<void(Address, ID)> callback)
     }
 }
 
-MMIOSegment::MMIOSegment(PhysicalAddress segment_base_addr, u8 start_bus, u8 end_bus)
+MMIOAccess::MMIOSegment::MMIOSegment(PhysicalAddress segment_base_addr, u8 start_bus, u8 end_bus)
     : m_base_addr(segment_base_addr)
     , m_start_bus(start_bus)
     , m_end_bus(end_bus)
 {
 }
 
-u8 MMIOSegment::get_start_bus() const
+u8 MMIOAccess::MMIOSegment::get_start_bus() const
 {
     return m_start_bus;
 }
 
-u8 MMIOSegment::get_end_bus() const
+u8 MMIOAccess::MMIOSegment::get_end_bus() const
 {
     return m_end_bus;
 }
 
-size_t MMIOSegment::get_size() const
+size_t MMIOAccess::MMIOSegment::get_size() const
 {
     return (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS * (get_end_bus() - get_start_bus()));
 }
 
-PhysicalAddress MMIOSegment::get_paddr() const
+PhysicalAddress MMIOAccess::MMIOSegment::get_paddr() const
 {
     return m_base_addr;
 }

Kernel/PCI/MMIOAccess.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
+ * Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,6 +32,7 @@
 #include <AK/Types.h>
 #include <Kernel/ACPI/Definitions.h>
 #include <Kernel/PCI/Access.h>
+#include <Kernel/SpinLock.h>
 #include <Kernel/VM/AnonymousVMObject.h>
 #include <Kernel/VM/PhysicalRegion.h>
 #include <Kernel/VM/Region.h>
@@ -40,27 +41,37 @@
 namespace Kernel {
 namespace PCI {
 
-class DeviceConfigurationSpaceMapping {
-public:
-    DeviceConfigurationSpaceMapping(Address, const MMIOSegment&);
-    VirtualAddress vaddr() const { return m_mapped_region->vaddr(); };
-    PhysicalAddress paddr() const { return m_mapped_region->physical_page(0)->paddr(); }
-    const Address& address() const { return m_device_address; };
-
-private:
-    Address m_device_address;
-    NonnullOwnPtr<Region> m_mapped_region;
-};
+#define PCI_MMIO_CONFIG_SPACE_SIZE 4096
 
-class MMIOAccess final : public Access {
+class MMIOAccess : public Access {
 public:
+    class MMIOSegment {
+    public:
+        MMIOSegment(PhysicalAddress, u8, u8);
+        u8 get_start_bus() const;
+        u8 get_end_bus() const;
+        size_t get_size() const;
+        PhysicalAddress get_paddr() const;
+
+    private:
+        PhysicalAddress m_base_addr;
+        u8 m_start_bus;
+        u8 m_end_bus;
+    };
     static void initialize(PhysicalAddress mcfg);
 
+private:
+    PhysicalAddress determine_memory_mapped_bus_region(u32 segment, u8 bus) const;
+    void map_bus_region(u32, u8);
+    VirtualAddress get_device_configuration_space(Address address);
+    SpinLock<u8> m_access_lock;
+    u8 m_mapped_bus { 0 };
+    OwnPtr<Region> m_mapped_region;
+
 protected:
     explicit MMIOAccess(PhysicalAddress mcfg);
 
-private:
-    virtual const char* access_type() const override { return "MMIO-Access"; };
+    virtual const char* access_type() const override { return "MMIOAccess"; };
     virtual u32 segment_count() const override;
     virtual void enumerate_hardware(Function<void(Address, ID)>) override;
     virtual void write8_field(Address address, u32, u8) override;
@@ -70,13 +81,11 @@ private:
     virtual u16 read16_field(Address address, u32) override;
     virtual u32 read32_field(Address address, u32) override;
 
-    Optional<VirtualAddress> get_device_configuration_space(Address address);
     virtual u8 segment_start_bus(u32) const override;
     virtual u8 segment_end_bus(u32) const override;
 
     PhysicalAddress m_mcfg;
     HashMap<u16, MMIOSegment> m_segments;
-    NonnullOwnPtrVector<DeviceConfigurationSpaceMapping> m_mapped_device_regions;
 };
 
 }

Kernel/PCI/WindowedMMIOAccess.cpp

@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2020-2021, Liav A. <liavalb@hotmail.co.il>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <AK/Optional.h>
+#include <AK/StringView.h>
+#include <Kernel/Debug.h>
+#include <Kernel/PCI/WindowedMMIOAccess.h>
+#include <Kernel/VM/MemoryManager.h>
+
+namespace Kernel {
+namespace PCI {
+
+UNMAP_AFTER_INIT DeviceConfigurationSpaceMapping::DeviceConfigurationSpaceMapping(Address device_address, const MMIOAccess::MMIOSegment& mmio_segment)
+    : m_device_address(device_address)
+    , m_mapped_region(MM.allocate_kernel_region(page_round_up(PCI_MMIO_CONFIG_SPACE_SIZE), "PCI MMIO Device Access", Region::Access::Read | Region::Access::Write).release_nonnull())
+{
+    PhysicalAddress segment_lower_addr = mmio_segment.get_paddr();
+    PhysicalAddress device_physical_mmio_space = segment_lower_addr.offset(
+        PCI_MMIO_CONFIG_SPACE_SIZE * m_device_address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * m_device_address.device() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS) * (m_device_address.bus() - mmio_segment.get_start_bus()));
+    m_mapped_region->physical_page_slot(0) = PhysicalPage::create(device_physical_mmio_space, false, false);
+    m_mapped_region->remap();
+}
+
+UNMAP_AFTER_INIT void WindowedMMIOAccess::initialize(PhysicalAddress mcfg)
+{
+    if (!Access::is_initialized()) {
+        new WindowedMMIOAccess(mcfg);
+        dbgln_if(PCI_DEBUG, "PCI: MMIO access initialised.");
+    }
+}
+
+UNMAP_AFTER_INIT WindowedMMIOAccess::WindowedMMIOAccess(PhysicalAddress p_mcfg)
+    : MMIOAccess(p_mcfg)
+{
+    dmesgln("PCI: Using MMIO (mapping per device) for PCI configuration space access");
+
+    InterruptDisabler disabler;
+
+    enumerate_hardware([&](const Address& address, ID) {
+        m_mapped_device_regions.append(make<DeviceConfigurationSpaceMapping>(address, m_segments.get(address.seg()).value()));
+    });
+}
+
+Optional<VirtualAddress> WindowedMMIOAccess::get_device_configuration_space(Address address)
+{
+    dbgln_if(PCI_DEBUG, "PCI: Getting device configuration space for {}", address);
+    for (auto& mapping : m_mapped_device_regions) {
+        auto checked_address = mapping.address();
+        dbgln_if(PCI_DEBUG, "PCI Device Configuration Space Mapping: Check if {} was requested", checked_address);
+        if (address.seg() == checked_address.seg()
+            && address.bus() == checked_address.bus()
+            && address.device() == checked_address.device()
+            && address.function() == checked_address.function()) {
+            dbgln_if(PCI_DEBUG, "PCI Device Configuration Space Mapping: Found {}", checked_address);
+            return mapping.vaddr();
+        }
+    }
+
+    dbgln_if(PCI_DEBUG, "PCI: No device configuration space found for {}", address);
+    return {};
+}
+
+u8 WindowedMMIOAccess::read8_field(Address address, u32 field)
+{
+    InterruptDisabler disabler;
+    VERIFY(field <= 0xfff);
+    dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 8-bit field {:#08x} for {}", field, address);
+    return *((u8*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
+}
+
+u16 WindowedMMIOAccess::read16_field(Address address, u32 field)
+{
+    InterruptDisabler disabler;
+    VERIFY(field < 0xfff);
+    dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 16-bit field {:#08x} for {}", field, address);
+    return *((u16*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
+}
+
+u32 WindowedMMIOAccess::read32_field(Address address, u32 field)
+{
+    InterruptDisabler disabler;
+    VERIFY(field <= 0xffc);
+    dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 32-bit field {:#08x} for {}", field, address);
+    return *((u32*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
+}
+
+void WindowedMMIOAccess::write8_field(Address address, u32 field, u8 value)
+{
+    InterruptDisabler disabler;
+    VERIFY(field <= 0xfff);
+    dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 8-bit field {:#08x}, value={:#02x} for {}", field, value, address);
+    *((u8*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
+}
+void WindowedMMIOAccess::write16_field(Address address, u32 field, u16 value)
+{
+    InterruptDisabler disabler;
+    VERIFY(field < 0xfff);
+    dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 16-bit field {:#08x}, value={:#02x} for {}", field, value, address);
+    *((u16*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
+}
+void WindowedMMIOAccess::write32_field(Address address, u32 field, u32 value)
+{
+    InterruptDisabler disabler;
+    VERIFY(field <= 0xffc);
+    dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 32-bit field {:#08x}, value={:#02x} for {}", field, value, address);
+    *((u32*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
+}
+
+}
+}

Kernel/PCI/WindowedMMIOAccess.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2020-2021, Liav A. <liavalb@hotmail.co.il>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#pragma once
+
+#include <AK/HashMap.h>
+#include <AK/NonnullOwnPtrVector.h>
+#include <AK/OwnPtr.h>
+#include <AK/Types.h>
+#include <Kernel/ACPI/Definitions.h>
+#include <Kernel/PCI/Access.h>
+#include <Kernel/PCI/MMIOAccess.h>
+#include <Kernel/VM/AnonymousVMObject.h>
+#include <Kernel/VM/PhysicalRegion.h>
+#include <Kernel/VM/Region.h>
+#include <Kernel/VM/VMObject.h>
+
+namespace Kernel {
+namespace PCI {
+
+class DeviceConfigurationSpaceMapping {
+public:
+    DeviceConfigurationSpaceMapping(Address, const MMIOAccess::MMIOSegment&);
+    VirtualAddress vaddr() const { return m_mapped_region->vaddr(); };
+    PhysicalAddress paddr() const { return m_mapped_region->physical_page(0)->paddr(); }
+    const Address& address() const { return m_device_address; };
+
+private:
+    Address m_device_address;
+    NonnullOwnPtr<Region> m_mapped_region;
+};
+
+class WindowedMMIOAccess final : public MMIOAccess {
+public:
+    static void initialize(PhysicalAddress mcfg);
+
+private:
+    explicit WindowedMMIOAccess(PhysicalAddress mcfg);
+    virtual const char* access_type() const override { return "WindowedMMIOAccess"; };
+    virtual void write8_field(Address address, u32, u8) override;
+    virtual void write16_field(Address address, u32, u16) override;
+    virtual void write32_field(Address address, u32, u32) override;
+    virtual u8 read8_field(Address address, u32) override;
+    virtual u16 read16_field(Address address, u32) override;
+    virtual u32 read32_field(Address address, u32) override;
+
+    Optional<VirtualAddress> get_device_configuration_space(Address address);
+    NonnullOwnPtrVector<DeviceConfigurationSpaceMapping> m_mapped_device_regions;
+};
+
+}
+}