Kernel/aarch64: Remove tpidr_el0 from RegisterState

In the next commit, this register will be populated by directly writing
to it, instead of using the RegisterState mechanism.

Kernel/Arch/aarch64/Interrupts.cpp

@@ -42,7 +42,6 @@ void dump_registers(RegisterState const& regs)
 
     dbgln("Saved Program Status: (NZCV({:#b}) DAIF({:#b}) M({:#b})) / 0x{:x}", ((regs.spsr_el1 >> 28) & 0b1111), ((regs.spsr_el1 >> 6) & 0b1111), regs.spsr_el1 & 0b1111, regs.spsr_el1);
     dbgln("Exception Link Register: 0x{:x}", regs.elr_el1);
-    dbgln("Software Thread ID: 0x{:x}", regs.tpidr_el0);
     dbgln("Stack Pointer (EL0): 0x{:x}", regs.sp_el0);
 
     dbgln(" x0={:p}  x1={:p}  x2={:p}  x3={:p}  x4={:p}", regs.x[0], regs.x[1], regs.x[2], regs.x[3], regs.x[4]);

Kernel/Arch/aarch64/Processor.cpp

@@ -291,7 +291,6 @@ FlatPtr Processor::init_context(Thread& thread, bool leave_crit)
     eretframe.x[30] = FlatPtr(&exit_kernel_thread);
     eretframe.elr_el1 = thread_regs.elr_el1;
     eretframe.sp_el0 = thread_regs.sp_el0;
-    eretframe.tpidr_el0 = 0; // FIXME: Correctly initialize this when aarch64 has support for thread local storage.
     eretframe.spsr_el1 = thread_regs.spsr_el1;
 
     // Push a TrapFrame onto the stack

Kernel/Arch/aarch64/RegisterState.h

@@ -16,11 +16,10 @@ VALIDATE_IS_AARCH64()
 namespace Kernel {
 
 struct RegisterState {
-    u64 x[31];     // Saved general purpose registers
-    u64 spsr_el1;  // Save Processor Status Register, EL1
-    u64 elr_el1;   // Exception Link Register, EL1
-    u64 tpidr_el0; // EL0 thread ID
-    u64 sp_el0;    // EL0 stack pointer
+    u64 x[31];    // Saved general purpose registers
+    u64 spsr_el1; // Save Processor Status Register, EL1
+    u64 elr_el1;  // Exception Link Register, EL1
+    u64 sp_el0;   // EL0 stack pointer
 
     FlatPtr userspace_sp() const { return sp_el0; }
     void set_userspace_sp(FlatPtr value)

Kernel/Arch/aarch64/vector_table.S

@@ -6,11 +6,10 @@
 
 .section .text.vector_table
 
-#define REGISTER_STATE_SIZE 272
+#define REGISTER_STATE_SIZE 264
 #define SPSR_EL1_SLOT       (31 * 8)
 #define ELR_EL1_SLOT        (32 * 8)
-#define TPIDR_EL0_SLOT      (33 * 8)
-#define SP_EL0_SLOT         (34 * 8)
+#define SP_EL0_SLOT         (33 * 8)
 
 // Vector Table Entry macro. Each entry is aligned at 128 bytes, meaning we have
 // at most that many instructions.
@@ -58,8 +57,6 @@
     str x0, [sp, #SPSR_EL1_SLOT]
     mrs x0, elr_el1
     str x0, [sp, #ELR_EL1_SLOT]
-    mrs x0, tpidr_el0
-    str x0, [sp, #TPIDR_EL0_SLOT]
     mrs x0, sp_el0
     str x0, [sp, #SP_EL0_SLOT]
 
@@ -83,8 +80,6 @@
     msr spsr_el1, x0
     ldr x0, [sp, #ELR_EL1_SLOT]
     msr elr_el1, x0
-    ldr x0, [sp, #TPIDR_EL0_SLOT]
-    msr tpidr_el0, x0
     ldr x0, [sp, #SP_EL0_SLOT]
     msr sp_el0, x0