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@@ -42,17 +42,17 @@ namespace Kernel {
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#define PIC1_CTL 0xA0
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#define PIC1_CMD 0xA1
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-#define ICW1_ICW4 0x01 /* ICW4 (not) needed */
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-#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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+#define ICW1_ICW4 0x01 /* ICW4 (not) needed */
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+#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
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-#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
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-#define ICW1_INIT 0x10 /* Initialization - required! */
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+#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
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+#define ICW1_INIT 0x10 /* Initialization - required! */
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-#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
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-#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
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-#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
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+#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
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+#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
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+#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
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#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
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-#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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+#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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bool inline static is_all_masked(u16 reg)
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{
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@@ -226,7 +226,7 @@ UNMAP_AFTER_INIT void PIC::initialize()
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// ...except IRQ2, since that's needed for the master to let through slave interrupts.
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enable_vector(2);
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- klog() << "PIC(i8259): cascading mode, vectors 0x" << String::format("%x", IRQ_VECTOR_BASE) << "-0x" << String::format("%x", IRQ_VECTOR_BASE + 0xf);
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+ dmesgln("PIC: Cascading mode, vectors {:#02x}-{:#02x}", IRQ_VECTOR_BASE, IRQ_VECTOR_BASE + 0xf);
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}
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u16 PIC::get_isr() const
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