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@@ -108,6 +108,13 @@ namespace Kernel {
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#define PCI_Mass_Storage_Class 0x1
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#define PCI_Mass_Storage_Class 0x1
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#define PCI_IDE_Controller_Subclass 0x1
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#define PCI_IDE_Controller_Subclass 0x1
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+static AK::Singleton<Lock> s_pata_lock;
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+
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+static Lock& s_lock()
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+{
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+ return *s_pata_lock;
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+};
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+
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OwnPtr<PATAChannel> PATAChannel::create(ChannelType type, bool force_pio)
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OwnPtr<PATAChannel> PATAChannel::create(ChannelType type, bool force_pio)
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{
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{
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PCI::Address pci_address;
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PCI::Address pci_address;
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@@ -141,59 +148,10 @@ PATAChannel::~PATAChannel()
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{
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{
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}
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}
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-void PATAChannel::start_request(AsyncBlockDeviceRequest& request, bool use_dma, bool is_slave)
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+void PATAChannel::prepare_for_irq()
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{
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{
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- m_current_request = &request;
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- m_current_request_block_index = 0;
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- m_current_request_uses_dma = use_dma;
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- m_current_request_flushing_cache = false;
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-
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- if (request.request_type() == AsyncBlockDeviceRequest::Read) {
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- if (use_dma)
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- ata_read_sectors_with_dma(is_slave);
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- else
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- ata_read_sectors(is_slave);
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- } else {
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- if (use_dma)
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- ata_write_sectors_with_dma(is_slave);
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- else
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- ata_write_sectors(is_slave);
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- }
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-}
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-
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-void PATAChannel::complete_current_request(AsyncDeviceRequest::RequestResult result)
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-{
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- // NOTE: this may be called from the interrupt handler!
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- ASSERT(m_current_request);
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-
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- // Now schedule reading back the buffer as soon as we leave the irq handler.
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- // This is important so that we can safely write the buffer back,
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- // which could cause page faults. Note that this may be called immediately
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- // before Processor::deferred_call_queue returns!
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- Processor::deferred_call_queue([this, result]() {
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-#ifdef PATA_DEBUG
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- dbg() << "PATAChannel::complete_current_request result: " << result;
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-#endif
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- ASSERT(m_current_request);
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- auto& request = *m_current_request;
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- m_current_request = nullptr;
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-
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- if (m_current_request_uses_dma) {
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- if (result == AsyncDeviceRequest::Success) {
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- if (request.request_type() == AsyncBlockDeviceRequest::Read) {
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- if (!request.write_to_buffer(request.buffer(), m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * request.block_count())) {
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- request.complete(AsyncDeviceRequest::MemoryFault);
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- return;
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- }
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- }
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-
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- // I read somewhere that this may trigger a cache flush so let's do it.
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- m_bus_master_base.offset(2).out<u8>(m_bus_master_base.offset(2).in<u8>() | 0x6);
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- }
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- }
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-
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- request.complete(result);
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- });
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+ cli();
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+ enable_irq();
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}
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}
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void PATAChannel::initialize(bool force_pio)
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void PATAChannel::initialize(bool force_pio)
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@@ -217,6 +175,12 @@ static void print_ide_status(u8 status)
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klog() << "PATAChannel: print_ide_status: DRQ=" << ((status & ATA_SR_DRQ) != 0) << " BSY=" << ((status & ATA_SR_BSY) != 0) << " DRDY=" << ((status & ATA_SR_DRDY) != 0) << " DSC=" << ((status & ATA_SR_DSC) != 0) << " DF=" << ((status & ATA_SR_DF) != 0) << " CORR=" << ((status & ATA_SR_CORR) != 0) << " IDX=" << ((status & ATA_SR_IDX) != 0) << " ERR=" << ((status & ATA_SR_ERR) != 0);
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klog() << "PATAChannel: print_ide_status: DRQ=" << ((status & ATA_SR_DRQ) != 0) << " BSY=" << ((status & ATA_SR_BSY) != 0) << " DRDY=" << ((status & ATA_SR_DRDY) != 0) << " DSC=" << ((status & ATA_SR_DSC) != 0) << " DF=" << ((status & ATA_SR_DF) != 0) << " CORR=" << ((status & ATA_SR_CORR) != 0) << " IDX=" << ((status & ATA_SR_IDX) != 0) << " ERR=" << ((status & ATA_SR_ERR) != 0);
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}
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}
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+void PATAChannel::wait_for_irq()
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+{
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+ Thread::current()->wait_on(m_irq_queue, "PATAChannel");
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+ disable_irq();
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+}
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+
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void PATAChannel::handle_irq(const RegisterState&)
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void PATAChannel::handle_irq(const RegisterState&)
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{
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{
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u8 status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
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u8 status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
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@@ -232,63 +196,16 @@ void PATAChannel::handle_irq(const RegisterState&)
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return;
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return;
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}
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}
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-#ifdef PATA_DEBUG
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- klog() << "PATAChannel: interrupt: DRQ=" << ((status & ATA_SR_DRQ) != 0) << " BSY=" << ((status & ATA_SR_BSY) != 0) << " DRDY=" << ((status & ATA_SR_DRDY) != 0);
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-#endif
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-
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- bool received_all_irqs = m_current_request_uses_dma || m_current_request_block_index + 1 >= m_current_request->block_count();
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-
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- disable_irq();
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-
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if (status & ATA_SR_ERR) {
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if (status & ATA_SR_ERR) {
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print_ide_status(status);
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print_ide_status(status);
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m_device_error = m_io_base.offset(ATA_REG_ERROR).in<u8>();
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m_device_error = m_io_base.offset(ATA_REG_ERROR).in<u8>();
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klog() << "PATAChannel: Error " << String::format("%b", m_device_error) << "!";
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klog() << "PATAChannel: Error " << String::format("%b", m_device_error) << "!";
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- complete_current_request(AsyncDeviceRequest::Failure);
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- return;
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- }
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-
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- m_device_error = 0;
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- if (received_all_irqs) {
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- complete_current_request(AsyncDeviceRequest::Success);
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} else {
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} else {
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- ASSERT(!m_current_request_uses_dma);
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-
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- // Now schedule reading/writing the buffer as soon as we leave the irq handler.
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- // This is important so that we can safely access the buffers, which could
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- // trigger page faults
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- Processor::deferred_call_queue([this]() {
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- if (m_current_request->request_type() == AsyncBlockDeviceRequest::Read) {
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- dbg() << "PATAChannel: Read block " << m_current_request_block_index << "/" << m_current_request->block_count();
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- if (ata_do_read_sector()) {
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- if (++m_current_request_block_index >= m_current_request->block_count()) {
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- complete_current_request(AsyncDeviceRequest::Success);
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- return;
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- }
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- // Wait for the next block
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- enable_irq();
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- }
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- } else {
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- if (!m_current_request_flushing_cache) {
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- dbg() << "PATAChannel: Wrote block " << m_current_request_block_index << "/" << m_current_request->block_count();
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- if (++m_current_request_block_index >= m_current_request->block_count()) {
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- // We read the last block, flush cache
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- ASSERT(!m_current_request_flushing_cache);
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- m_current_request_flushing_cache = true;
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- enable_irq();
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- m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_CACHE_FLUSH);
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- } else {
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- // Read next block
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- enable_irq();
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- ata_do_write_sector();
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- }
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- } else {
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- complete_current_request(AsyncDeviceRequest::Success);
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- }
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- }
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- });
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+ m_device_error = 0;
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}
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}
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-
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+#ifdef PATA_DEBUG
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+ klog() << "PATAChannel: interrupt: DRQ=" << ((status & ATA_SR_DRQ) != 0) << " BSY=" << ((status & ATA_SR_BSY) != 0) << " DRDY=" << ((status & ATA_SR_DRDY) != 0);
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+#endif
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m_irq_queue.wake_all();
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m_irq_queue.wake_all();
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}
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}
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@@ -357,16 +274,15 @@ void PATAChannel::detect_disks()
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}
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}
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}
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}
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-void PATAChannel::ata_read_sectors_with_dma(bool slave_request)
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+bool PATAChannel::ata_read_sectors_with_dma(u32 lba, u16 count, UserOrKernelBuffer& outbuf, bool slave_request)
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{
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{
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- auto& request = *m_current_request;
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- u32 lba = request.block_index();
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+ LOCKER(s_lock());
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#ifdef PATA_DEBUG
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#ifdef PATA_DEBUG
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- dbg() << "PATAChannel::ata_read_sectors_with_dma (" << lba << " x" << request.block_count() << ")";
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+ dbg() << "PATAChannel::ata_read_sectors_with_dma (" << lba << " x" << count << ") -> " << outbuf.user_or_kernel_ptr();
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#endif
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#endif
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prdt().offset = m_dma_buffer_page->paddr();
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prdt().offset = m_dma_buffer_page->paddr();
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- prdt().size = 512 * request.block_count();
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+ prdt().size = 512 * count;
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ASSERT(prdt().size <= PAGE_SIZE);
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ASSERT(prdt().size <= PAGE_SIZE);
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@@ -396,7 +312,7 @@ void PATAChannel::ata_read_sectors_with_dma(bool slave_request)
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m_io_base.offset(ATA_REG_LBA1).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA1).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA2).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA2).out<u8>(0);
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- m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(request.block_count());
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+ m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(count);
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m_io_base.offset(ATA_REG_LBA0).out<u8>((lba & 0x000000ff) >> 0);
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m_io_base.offset(ATA_REG_LBA0).out<u8>((lba & 0x000000ff) >> 0);
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m_io_base.offset(ATA_REG_LBA1).out<u8>((lba & 0x0000ff00) >> 8);
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m_io_base.offset(ATA_REG_LBA1).out<u8>((lba & 0x0000ff00) >> 8);
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m_io_base.offset(ATA_REG_LBA2).out<u8>((lba & 0x00ff0000) >> 16);
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m_io_base.offset(ATA_REG_LBA2).out<u8>((lba & 0x00ff0000) >> 16);
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@@ -410,60 +326,62 @@ void PATAChannel::ata_read_sectors_with_dma(bool slave_request)
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m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_READ_DMA_EXT);
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m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_READ_DMA_EXT);
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io_delay();
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io_delay();
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- enable_irq();
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+ prepare_for_irq();
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// Start bus master
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// Start bus master
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m_bus_master_base.out<u8>(0x9);
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m_bus_master_base.out<u8>(0x9);
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-}
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-bool PATAChannel::ata_do_read_sector()
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-{
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- auto& request = *m_current_request;
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- auto out_buffer = request.buffer().offset(m_current_request_block_index * 512);
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- ssize_t nwritten = request.write_to_buffer_buffered<512>(out_buffer, 512, [&](u8* buffer, size_t buffer_bytes) {
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- for (size_t i = 0; i < buffer_bytes; i += sizeof(u16))
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- *(u16*)&buffer[i] = IO::in16(m_io_base.offset(ATA_REG_DATA).get());
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- return (ssize_t)buffer_bytes;
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- });
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- if (nwritten < 0) {
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- // TODO: Do we need to abort the PATA read if this wasn't the last block?
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- complete_current_request(AsyncDeviceRequest::MemoryFault);
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+ wait_for_irq();
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+
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+ if (m_device_error)
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return false;
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return false;
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- }
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+
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+ if (!outbuf.write(m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * count))
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+ return false; // TODO: -EFAULT
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+
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+ // I read somewhere that this may trigger a cache flush so let's do it.
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+ m_bus_master_base.offset(2).out<u8>(m_bus_master_base.offset(2).in<u8>() | 0x6);
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return true;
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return true;
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}
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}
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-void PATAChannel::ata_read_sectors(bool slave_request)
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+bool PATAChannel::ata_write_sectors_with_dma(u32 lba, u16 count, const UserOrKernelBuffer& inbuf, bool slave_request)
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{
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{
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- auto& request = *m_current_request;
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- ASSERT(request.block_count() <= 256);
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+ LOCKER(s_lock());
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#ifdef PATA_DEBUG
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#ifdef PATA_DEBUG
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- dbg() << "PATAChannel::ata_read_sectors";
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+ dbg() << "PATAChannel::ata_write_sectors_with_dma (" << lba << " x" << count << ") <- " << inbuf.user_or_kernel_ptr();
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#endif
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#endif
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- while (m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY)
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- ;
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+ prdt().offset = m_dma_buffer_page->paddr();
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+ prdt().size = 512 * count;
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- auto lba = request.block_index();
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-#ifdef PATA_DEBUG
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- klog() << "PATAChannel: Reading " << request.block_count() << " sector(s) @ LBA " << lba;
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-#endif
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+ if (!inbuf.read(m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * count))
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+ return false; // TODO: -EFAULT
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- u8 devsel = 0xe0;
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- if (slave_request)
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- devsel |= 0x10;
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+ ASSERT(prdt().size <= PAGE_SIZE);
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+
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+ // Stop bus master
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+ m_bus_master_base.out<u8>(0);
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+
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+ // Write the PRDT location
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+ m_bus_master_base.offset(4).out<u32>(m_prdt_page->paddr().get());
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+
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+ // Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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+ m_bus_master_base.offset(2).out<u8>(m_bus_master_base.offset(2).in<u8>() | 0x6);
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+
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+ while (m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY)
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+ ;
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m_control_base.offset(ATA_CTL_CONTROL).out<u8>(0);
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m_control_base.offset(ATA_CTL_CONTROL).out<u8>(0);
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- m_io_base.offset(ATA_REG_HDDEVSEL).out<u8>(devsel | (static_cast<u8>(slave_request) << 4) | 0x40);
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+ m_io_base.offset(ATA_REG_HDDEVSEL).out<u8>(0x40 | (static_cast<u8>(slave_request) << 4));
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io_delay();
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io_delay();
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- m_io_base.offset(ATA_REG_FEATURES).out<u8>(0);
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+ m_io_base.offset(ATA_REG_FEATURES).out<u16>(0);
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m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(0);
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m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA0).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA0).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA1).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA1).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA2).out<u8>(0);
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m_io_base.offset(ATA_REG_LBA2).out<u8>(0);
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- m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(request.block_count());
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+ m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(count);
|
|
m_io_base.offset(ATA_REG_LBA0).out<u8>((lba & 0x000000ff) >> 0);
|
|
m_io_base.offset(ATA_REG_LBA0).out<u8>((lba & 0x000000ff) >> 0);
|
|
m_io_base.offset(ATA_REG_LBA1).out<u8>((lba & 0x0000ff00) >> 8);
|
|
m_io_base.offset(ATA_REG_LBA1).out<u8>((lba & 0x0000ff00) >> 8);
|
|
m_io_base.offset(ATA_REG_LBA2).out<u8>((lba & 0x00ff0000) >> 16);
|
|
m_io_base.offset(ATA_REG_LBA2).out<u8>((lba & 0x00ff0000) >> 16);
|
|
@@ -474,52 +392,53 @@ void PATAChannel::ata_read_sectors(bool slave_request)
|
|
break;
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
- enable_irq();
|
|
|
|
- m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_READ_PIO);
|
|
|
|
|
|
+ m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_WRITE_DMA_EXT);
|
|
|
|
+ io_delay();
|
|
|
|
+
|
|
|
|
+ prepare_for_irq();
|
|
|
|
+ // Start bus master
|
|
|
|
+ m_bus_master_base.out<u8>(0x1);
|
|
|
|
+ wait_for_irq();
|
|
|
|
+
|
|
|
|
+ if (m_device_error)
|
|
|
|
+ return false;
|
|
|
|
+
|
|
|
|
+ // I read somewhere that this may trigger a cache flush so let's do it.
|
|
|
|
+ m_bus_master_base.offset(2).out<u8>(m_bus_master_base.offset(2).in<u8>() | 0x6);
|
|
|
|
+ return true;
|
|
}
|
|
}
|
|
|
|
|
|
-void PATAChannel::ata_write_sectors_with_dma(bool slave_request)
|
|
|
|
|
|
+bool PATAChannel::ata_read_sectors(u32 lba, u16 count, UserOrKernelBuffer& outbuf, bool slave_request)
|
|
{
|
|
{
|
|
- auto& request = *m_current_request;
|
|
|
|
- u32 lba = request.block_index();
|
|
|
|
|
|
+ ASSERT(count <= 256);
|
|
|
|
+ LOCKER(s_lock());
|
|
#ifdef PATA_DEBUG
|
|
#ifdef PATA_DEBUG
|
|
- dbg() << "PATAChannel::ata_write_sectors_with_dma (" << lba << " x" << request.block_count() << ")";
|
|
|
|
|
|
+ dbg() << "PATAChannel::ata_read_sectors request (" << count << " sector(s) @ " << lba << " into " << outbuf.user_or_kernel_ptr() << ")";
|
|
#endif
|
|
#endif
|
|
|
|
|
|
- prdt().offset = m_dma_buffer_page->paddr();
|
|
|
|
- prdt().size = 512 * request.block_count();
|
|
|
|
-
|
|
|
|
- if (!request.read_from_buffer(request.buffer(), m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * request.block_count())) {
|
|
|
|
- complete_current_request(AsyncDeviceRequest::MemoryFault);
|
|
|
|
- return;
|
|
|
|
- }
|
|
|
|
-
|
|
|
|
- ASSERT(prdt().size <= PAGE_SIZE);
|
|
|
|
-
|
|
|
|
- // Stop bus master
|
|
|
|
- m_bus_master_base.out<u8>(0);
|
|
|
|
-
|
|
|
|
- // Write the PRDT location
|
|
|
|
- m_bus_master_base.offset(4).out<u32>(m_prdt_page->paddr().get());
|
|
|
|
-
|
|
|
|
- // Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
|
|
|
|
- m_bus_master_base.offset(2).out<u8>(m_bus_master_base.offset(2).in<u8>() | 0x6);
|
|
|
|
-
|
|
|
|
while (m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY)
|
|
while (m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY)
|
|
;
|
|
;
|
|
|
|
|
|
|
|
+#ifdef PATA_DEBUG
|
|
|
|
+ klog() << "PATAChannel: Reading " << count << " sector(s) @ LBA " << lba;
|
|
|
|
+#endif
|
|
|
|
+
|
|
|
|
+ u8 devsel = 0xe0;
|
|
|
|
+ if (slave_request)
|
|
|
|
+ devsel |= 0x10;
|
|
|
|
+
|
|
m_control_base.offset(ATA_CTL_CONTROL).out<u8>(0);
|
|
m_control_base.offset(ATA_CTL_CONTROL).out<u8>(0);
|
|
- m_io_base.offset(ATA_REG_HDDEVSEL).out<u8>(0x40 | (static_cast<u8>(slave_request) << 4));
|
|
|
|
|
|
+ m_io_base.offset(ATA_REG_HDDEVSEL).out<u8>(devsel | (static_cast<u8>(slave_request) << 4) | 0x40);
|
|
io_delay();
|
|
io_delay();
|
|
|
|
|
|
- m_io_base.offset(ATA_REG_FEATURES).out<u16>(0);
|
|
|
|
|
|
+ m_io_base.offset(ATA_REG_FEATURES).out<u8>(0);
|
|
|
|
|
|
m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(0);
|
|
m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(0);
|
|
m_io_base.offset(ATA_REG_LBA0).out<u8>(0);
|
|
m_io_base.offset(ATA_REG_LBA0).out<u8>(0);
|
|
m_io_base.offset(ATA_REG_LBA1).out<u8>(0);
|
|
m_io_base.offset(ATA_REG_LBA1).out<u8>(0);
|
|
m_io_base.offset(ATA_REG_LBA2).out<u8>(0);
|
|
m_io_base.offset(ATA_REG_LBA2).out<u8>(0);
|
|
|
|
|
|
- m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(request.block_count());
|
|
|
|
|
|
+ m_io_base.offset(ATA_REG_SECCOUNT0).out<u8>(count);
|
|
m_io_base.offset(ATA_REG_LBA0).out<u8>((lba & 0x000000ff) >> 0);
|
|
m_io_base.offset(ATA_REG_LBA0).out<u8>((lba & 0x000000ff) >> 0);
|
|
m_io_base.offset(ATA_REG_LBA1).out<u8>((lba & 0x0000ff00) >> 8);
|
|
m_io_base.offset(ATA_REG_LBA1).out<u8>((lba & 0x0000ff00) >> 8);
|
|
m_io_base.offset(ATA_REG_LBA2).out<u8>((lba & 0x00ff0000) >> 16);
|
|
m_io_base.offset(ATA_REG_LBA2).out<u8>((lba & 0x00ff0000) >> 16);
|
|
@@ -530,45 +449,46 @@ void PATAChannel::ata_write_sectors_with_dma(bool slave_request)
|
|
break;
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
- m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_WRITE_DMA_EXT);
|
|
|
|
- io_delay();
|
|
|
|
-
|
|
|
|
- enable_irq();
|
|
|
|
- // Start bus master
|
|
|
|
- m_bus_master_base.out<u8>(0x1);
|
|
|
|
-}
|
|
|
|
-
|
|
|
|
-void PATAChannel::ata_do_write_sector()
|
|
|
|
-{
|
|
|
|
- auto& request = *m_current_request;
|
|
|
|
|
|
+ prepare_for_irq();
|
|
|
|
+ m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_READ_PIO);
|
|
|
|
|
|
- io_delay();
|
|
|
|
- while ((m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY) || !(m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_DRQ))
|
|
|
|
- ;
|
|
|
|
|
|
+ for (int i = 0; i < count; i++) {
|
|
|
|
+ if (i > 0)
|
|
|
|
+ prepare_for_irq();
|
|
|
|
+ wait_for_irq();
|
|
|
|
+ if (m_device_error)
|
|
|
|
+ return false;
|
|
|
|
|
|
- u8 status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
|
|
|
|
- ASSERT(status & ATA_SR_DRQ);
|
|
|
|
|
|
+ u8 status = m_control_base.offset(ATA_CTL_ALTSTATUS).in<u8>();
|
|
|
|
+ ASSERT(!(status & ATA_SR_BSY));
|
|
|
|
|
|
- auto in_buffer = request.buffer().offset(m_current_request_block_index * 512);
|
|
|
|
|
|
+ auto out = outbuf.offset(i * 512);
|
|
#ifdef PATA_DEBUG
|
|
#ifdef PATA_DEBUG
|
|
- dbg() << "PATAChannel: Writing 512 bytes (part " << m_current_request_block_index << ") (status=" << String::format("%b", status) << ")...";
|
|
|
|
|
|
+ dbg() << "PATAChannel: Retrieving 512 bytes (part " << i << ") (status=" << String::format("%b", status) << "), outbuf=(" << out.user_or_kernel_ptr() << ")...";
|
|
#endif
|
|
#endif
|
|
- ssize_t nread = request.read_from_buffer_buffered<512>(in_buffer, 512, [&](const u8* buffer, size_t buffer_bytes) {
|
|
|
|
- for (size_t i = 0; i < buffer_bytes; i += sizeof(u16))
|
|
|
|
- IO::out16(m_io_base.offset(ATA_REG_DATA).get(), *(const u16*)&buffer[i]);
|
|
|
|
- return (ssize_t)buffer_bytes;
|
|
|
|
- });
|
|
|
|
- if (nread < 0)
|
|
|
|
- complete_current_request(AsyncDeviceRequest::MemoryFault);
|
|
|
|
|
|
+ prepare_for_irq();
|
|
|
|
+
|
|
|
|
+ ssize_t nwritten = out.write_buffered<512>(512, [&](u8* buffer, size_t buffer_bytes) {
|
|
|
|
+ for (size_t i = 0; i < buffer_bytes; i += sizeof(u16))
|
|
|
|
+ *(u16*)&buffer[i] = IO::in16(m_io_base.offset(ATA_REG_DATA).get());
|
|
|
|
+ return (ssize_t)buffer_bytes;
|
|
|
|
+ });
|
|
|
|
+ if (nwritten < 0) {
|
|
|
|
+ sti();
|
|
|
|
+ disable_irq();
|
|
|
|
+ return false; // TODO: -EFAULT
|
|
|
|
+ }
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ sti();
|
|
|
|
+ disable_irq();
|
|
|
|
+ return true;
|
|
}
|
|
}
|
|
|
|
|
|
-void PATAChannel::ata_write_sectors(bool slave_request)
|
|
|
|
|
|
+bool PATAChannel::ata_write_sectors(u32 start_sector, u16 count, const UserOrKernelBuffer& inbuf, bool slave_request)
|
|
{
|
|
{
|
|
- auto& request = *m_current_request;
|
|
|
|
-
|
|
|
|
- ASSERT(request.block_count() <= 256);
|
|
|
|
- u32 start_sector = request.block_index();
|
|
|
|
- u32 count = request.block_count();
|
|
|
|
|
|
+ ASSERT(count <= 256);
|
|
|
|
+ LOCKER(s_lock());
|
|
#ifdef PATA_DEBUG
|
|
#ifdef PATA_DEBUG
|
|
klog() << "PATAChannel::ata_write_sectors request (" << count << " sector(s) @ " << start_sector << ")";
|
|
klog() << "PATAChannel::ata_write_sectors request (" << count << " sector(s) @ " << start_sector << ")";
|
|
#endif
|
|
#endif
|
|
@@ -596,12 +516,37 @@ void PATAChannel::ata_write_sectors(bool slave_request)
|
|
|
|
|
|
m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_WRITE_PIO);
|
|
m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_WRITE_PIO);
|
|
|
|
|
|
- io_delay();
|
|
|
|
- while ((m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY) || !(m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_DRQ))
|
|
|
|
- ;
|
|
|
|
|
|
+ for (int i = 0; i < count; i++) {
|
|
|
|
+ io_delay();
|
|
|
|
+ while ((m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_BSY) || !(m_io_base.offset(ATA_REG_STATUS).in<u8>() & ATA_SR_DRQ))
|
|
|
|
+ ;
|
|
|
|
|
|
- enable_irq();
|
|
|
|
- ata_do_write_sector();
|
|
|
|
|
|
+ u8 status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
|
|
|
|
+ ASSERT(status & ATA_SR_DRQ);
|
|
|
|
+
|
|
|
|
+ auto in = inbuf.offset(i * 512);
|
|
|
|
+#ifdef PATA_DEBUG
|
|
|
|
+ dbg() << "PATAChannel: Writing 512 bytes (part " << i << ") (status=" << String::format("%b", status) << "), inbuf=(" << in.user_or_kernel_ptr() << ")...";
|
|
|
|
+#endif
|
|
|
|
+ prepare_for_irq();
|
|
|
|
+ ssize_t nread = in.read_buffered<512>(512, [&](const u8* buffer, size_t buffer_bytes) {
|
|
|
|
+ for (size_t i = 0; i < buffer_bytes; i += sizeof(u16))
|
|
|
|
+ IO::out16(m_io_base.offset(ATA_REG_DATA).get(), *(const u16*)&buffer[i]);
|
|
|
|
+ return (ssize_t)buffer_bytes;
|
|
|
|
+ });
|
|
|
|
+ wait_for_irq();
|
|
|
|
+ status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
|
|
|
|
+ ASSERT(!(status & ATA_SR_BSY));
|
|
|
|
+ if (nread < 0)
|
|
|
|
+ return false; // TODO: -EFAULT
|
|
|
|
+ }
|
|
|
|
+ prepare_for_irq();
|
|
|
|
+ m_io_base.offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_CACHE_FLUSH);
|
|
|
|
+ wait_for_irq();
|
|
|
|
+ u8 status = m_io_base.offset(ATA_REG_STATUS).in<u8>();
|
|
|
|
+ ASSERT(!(status & ATA_SR_BSY));
|
|
|
|
+
|
|
|
|
+ return !m_device_error;
|
|
}
|
|
}
|
|
|
|
|
|
}
|
|
}
|