Kernel: Oops, actually enable CR4.PGE (page table global bit)

Turns out we were setting the wrong bit here. Now we will actually keep
kernel memory mappings in the TLB across context switches.

Kernel/VM/MemoryManager.cpp

@@ -168,7 +168,7 @@ void MemoryManager::initialize_paging()
     // Turn on CR4.PGE so the CPU will respect the G bit in page tables.
     asm volatile(
         "mov %cr4, %eax\n"
-        "orl $0x10, %eax\n"
+        "orl $0x40, %eax\n"
         "mov %eax, %cr4\n");
 
     asm volatile("movl %%eax, %%cr3" ::"a"(kernel_page_directory().cr3()));