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@@ -166,15 +166,15 @@ static typename TypeDoubler<Destination>::type op_xor(SoftCPU& cpu, const Destin
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if constexpr (sizeof(Destination) == 4) {
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asm volatile("xorl %%ecx, %%eax\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u32)src));
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} else if constexpr (sizeof(Destination) == 2) {
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asm volatile("xor %%cx, %%ax\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u16)src));
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} else if constexpr (sizeof(Destination) == 1) {
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asm volatile("xorb %%cl, %%al\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u8)src));
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} else {
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ASSERT_NOT_REACHED();
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}
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@@ -197,15 +197,15 @@ static typename TypeDoubler<Destination>::type op_sub(SoftCPU& cpu, const Destin
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if constexpr (sizeof(Destination) == 4) {
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asm volatile("subl %%ecx, %%eax\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u32)src));
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} else if constexpr (sizeof(Destination) == 2) {
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asm volatile("subw %%cx, %%ax\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u16)src));
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} else if constexpr (sizeof(Destination) == 1) {
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asm volatile("subb %%cl, %%al\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u8)src));
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} else {
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ASSERT_NOT_REACHED();
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}
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@@ -228,15 +228,15 @@ static Destination op_add(SoftCPU& cpu, Destination& dest, const Source& src)
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if constexpr (sizeof(Destination) == 4) {
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asm volatile("addl %%ecx, %%eax\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u32)src));
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} else if constexpr (sizeof(Destination) == 2) {
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asm volatile("addw %%cx, %%ax\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u16)src));
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} else if constexpr (sizeof(Destination) == 1) {
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asm volatile("addb %%cl, %%al\n"
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: "=a"(result)
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- : "a"(dest), "c"(src));
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+ : "a"(dest), "c"((u8)src));
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} else {
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ASSERT_NOT_REACHED();
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}
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