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@@ -1573,11 +1573,42 @@ void SoftCPU::WBINVD(const X86::Instruction&) { TODO(); }
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void SoftCPU::XADD_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::XADD_RM32_reg32(const X86::Instruction&) { TODO(); }
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void SoftCPU::XADD_RM8_reg8(const X86::Instruction&) { TODO(); }
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-void SoftCPU::XCHG_AX_reg16(const X86::Instruction&) { TODO(); }
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-void SoftCPU::XCHG_EAX_reg32(const X86::Instruction&) { TODO(); }
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-void SoftCPU::XCHG_reg16_RM16(const X86::Instruction&) { TODO(); }
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-void SoftCPU::XCHG_reg32_RM32(const X86::Instruction&) { TODO(); }
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-void SoftCPU::XCHG_reg8_RM8(const X86::Instruction&) { TODO(); }
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+
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+void SoftCPU::XCHG_AX_reg16(const X86::Instruction& insn)
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+{
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+ auto temp = gpr16(insn.reg16());
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+ gpr16(insn.reg16()) = eax();
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+ set_eax(temp);
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+}
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+
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+void SoftCPU::XCHG_EAX_reg32(const X86::Instruction& insn)
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+{
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+ auto temp = gpr32(insn.reg32());
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+ gpr32(insn.reg32()) = eax();
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+ set_eax(temp);
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+}
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+
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+void SoftCPU::XCHG_reg16_RM16(const X86::Instruction& insn)
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+{
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+ auto temp = insn.modrm().read16(*this, insn);
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+ insn.modrm().write16(*this, insn, gpr16(insn.reg16()));
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+ gpr16(insn.reg16()) = temp;
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+}
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+
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+void SoftCPU::XCHG_reg32_RM32(const X86::Instruction& insn)
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+{
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+ auto temp = insn.modrm().read32(*this, insn);
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+ insn.modrm().write32(*this, insn, gpr32(insn.reg32()));
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+ gpr32(insn.reg32()) = temp;
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+}
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+
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+void SoftCPU::XCHG_reg8_RM8(const X86::Instruction& insn)
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+{
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+ auto temp = insn.modrm().read8(*this, insn);
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+ insn.modrm().write8(*this, insn, gpr8(insn.reg8()));
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+ gpr8(insn.reg8()) = temp;
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+}
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+
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void SoftCPU::XLAT(const X86::Instruction&) { TODO(); }
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#define DEFINE_GENERIC_INSN_HANDLERS_PARTIAL(mnemonic, op, update_dest) \
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